^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * arch/xtensa/kernel/coprocessor.S
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Xtensa processor configuration-specific table of coprocessor and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * other custom register layout information.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * This file is subject to the terms and conditions of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * License. See the file "COPYING" in the main directory of this archive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Copyright (C) 2003 - 2007 Tensilica Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/linkage.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <asm/asm-offsets.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <asm/asmmacro.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <asm/coprocessor.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <asm/current.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <asm/regs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #if XTENSA_HAVE_COPROCESSORS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * Macros for lazy context switch.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define SAVE_CP_REGS(x) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) .if XTENSA_HAVE_COPROCESSOR(x); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) .align 4; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) .Lsave_cp_regs_cp##x: \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) xchal_cp##x##_store a2 a4 a5 a6 a7; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) jx a0; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) .endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define SAVE_CP_REGS_TAB(x) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) .if XTENSA_HAVE_COPROCESSOR(x); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) .long .Lsave_cp_regs_cp##x; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) .else; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) .long 0; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) .endif; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) .long THREAD_XTREGS_CP##x
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define LOAD_CP_REGS(x) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) .if XTENSA_HAVE_COPROCESSOR(x); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) .align 4; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) .Lload_cp_regs_cp##x: \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) xchal_cp##x##_load a2 a4 a5 a6 a7; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) jx a0; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) .endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define LOAD_CP_REGS_TAB(x) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) .if XTENSA_HAVE_COPROCESSOR(x); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) .long .Lload_cp_regs_cp##x; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) .else; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) .long 0; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) .endif; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) .long THREAD_XTREGS_CP##x
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) __XTENSA_HANDLER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) SAVE_CP_REGS(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) SAVE_CP_REGS(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) SAVE_CP_REGS(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) SAVE_CP_REGS(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) SAVE_CP_REGS(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) SAVE_CP_REGS(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) SAVE_CP_REGS(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) SAVE_CP_REGS(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) LOAD_CP_REGS(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) LOAD_CP_REGS(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) LOAD_CP_REGS(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) LOAD_CP_REGS(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) LOAD_CP_REGS(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) LOAD_CP_REGS(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) LOAD_CP_REGS(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) LOAD_CP_REGS(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) .align 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) .Lsave_cp_regs_jump_table:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) SAVE_CP_REGS_TAB(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) SAVE_CP_REGS_TAB(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) SAVE_CP_REGS_TAB(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) SAVE_CP_REGS_TAB(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) SAVE_CP_REGS_TAB(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) SAVE_CP_REGS_TAB(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) SAVE_CP_REGS_TAB(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) SAVE_CP_REGS_TAB(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) .Lload_cp_regs_jump_table:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) LOAD_CP_REGS_TAB(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) LOAD_CP_REGS_TAB(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) LOAD_CP_REGS_TAB(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) LOAD_CP_REGS_TAB(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) LOAD_CP_REGS_TAB(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) LOAD_CP_REGS_TAB(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) LOAD_CP_REGS_TAB(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) LOAD_CP_REGS_TAB(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) * Entry condition:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) * a0: trashed, original value saved on stack (PT_AREG0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) * a1: a1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) * a2: new stack pointer, original in DEPC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) * a3: a3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) * depc: a2, original value saved on stack (PT_DEPC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) * excsave_1: dispatch table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) * PT_DEPC >= VALID_DOUBLE_EXCEPTION_ADDRESS: double exception, DEPC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) * < VALID_DOUBLE_EXCEPTION_ADDRESS: regular exception
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) ENTRY(fast_coprocessor)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) /* Save remaining registers a1-a3 and SAR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) s32i a3, a2, PT_AREG3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) rsr a3, sar
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) s32i a1, a2, PT_AREG1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) s32i a3, a2, PT_SAR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) mov a1, a2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) rsr a2, depc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) s32i a2, a1, PT_AREG2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) * The hal macros require up to 4 temporary registers. We use a3..a6.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) s32i a4, a1, PT_AREG4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) s32i a5, a1, PT_AREG5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) s32i a6, a1, PT_AREG6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) /* Find coprocessor number. Subtract first CP EXCCAUSE from EXCCAUSE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) rsr a3, exccause
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) addi a3, a3, -EXCCAUSE_COPROCESSOR0_DISABLED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) /* Set corresponding CPENABLE bit -> (sar:cp-index, a3: 1<<cp-index)*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) ssl a3 # SAR: 32 - coprocessor_number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) movi a2, 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) rsr a0, cpenable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) sll a2, a2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) or a0, a0, a2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) wsr a0, cpenable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) rsync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) /* Retrieve previous owner. (a3 still holds CP number) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) movi a0, coprocessor_owner # list of owners
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) addx4 a0, a3, a0 # entry for CP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) l32i a4, a0, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) beqz a4, 1f # skip 'save' if no previous owner
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) /* Disable coprocessor for previous owner. (a2 = 1 << CP number) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) l32i a5, a4, THREAD_CPENABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) xor a5, a5, a2 # (1 << cp-id) still in a2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) s32i a5, a4, THREAD_CPENABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) * Get context save area and 'call' save routine.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) * (a4 still holds previous owner (thread_info), a3 CP number)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) movi a5, .Lsave_cp_regs_jump_table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) movi a0, 2f # a0: 'return' address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) addx8 a3, a3, a5 # a3: coprocessor number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) l32i a2, a3, 4 # a2: xtregs offset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) l32i a3, a3, 0 # a3: jump address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) add a2, a2, a4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) jx a3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) /* Note that only a0 and a1 were preserved. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 2: rsr a3, exccause
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) addi a3, a3, -EXCCAUSE_COPROCESSOR0_DISABLED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) movi a0, coprocessor_owner
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) addx4 a0, a3, a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) /* Set new 'owner' (a0 points to the CP owner, a3 contains the CP nr) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 1: GET_THREAD_INFO (a4, a1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) s32i a4, a0, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) /* Get context save area and 'call' load routine. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) movi a5, .Lload_cp_regs_jump_table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) movi a0, 1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) addx8 a3, a3, a5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) l32i a2, a3, 4 # a2: xtregs offset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) l32i a3, a3, 0 # a3: jump address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) add a2, a2, a4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) jx a3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) /* Restore all registers and return from exception handler. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 1: l32i a6, a1, PT_AREG6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) l32i a5, a1, PT_AREG5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) l32i a4, a1, PT_AREG4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) l32i a0, a1, PT_SAR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) l32i a3, a1, PT_AREG3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) l32i a2, a1, PT_AREG2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) wsr a0, sar
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) l32i a0, a1, PT_AREG0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) l32i a1, a1, PT_AREG1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) rfe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) ENDPROC(fast_coprocessor)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) .text
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) * coprocessor_flush(struct thread_info*, index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) * a2 a3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) * Save coprocessor registers for coprocessor 'index'.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) * The register values are saved to or loaded from the coprocessor area
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) * inside the task_info structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) * Note that this function doesn't update the coprocessor_owner information!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) ENTRY(coprocessor_flush)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) /* reserve 4 bytes on stack to save a0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) abi_entry(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) s32i a0, a1, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) movi a0, .Lsave_cp_regs_jump_table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) addx8 a3, a3, a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) l32i a4, a3, 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) l32i a3, a3, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) add a2, a2, a4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) beqz a3, 1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) callx0 a3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 1: l32i a0, a1, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) abi_ret(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) ENDPROC(coprocessor_flush)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) .data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) ENTRY(coprocessor_owner)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) .fill XCHAL_CP_MAX, 4, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) END(coprocessor_owner)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #endif /* XTENSA_HAVE_COPROCESSORS */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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