Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2)  * This file is subject to the terms and conditions of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * License.  See the file "COPYING" in the main directory of this archive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  * for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  * Copyright (C) 2001 - 2013 Tensilica Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #ifndef _XTENSA_TIMEX_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define _XTENSA_TIMEX_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <asm/processor.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #if XCHAL_NUM_TIMERS > 0 && \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 	XTENSA_INT_LEVEL(XCHAL_TIMER0_INTERRUPT) <= XCHAL_EXCM_LEVEL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) # define LINUX_TIMER     0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) # define LINUX_TIMER_INT XCHAL_TIMER0_INTERRUPT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #elif XCHAL_NUM_TIMERS > 1 && \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 	XTENSA_INT_LEVEL(XCHAL_TIMER1_INTERRUPT) <= XCHAL_EXCM_LEVEL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) # define LINUX_TIMER     1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) # define LINUX_TIMER_INT XCHAL_TIMER1_INTERRUPT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #elif XCHAL_NUM_TIMERS > 2 && \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 	XTENSA_INT_LEVEL(XCHAL_TIMER2_INTERRUPT) <= XCHAL_EXCM_LEVEL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) # define LINUX_TIMER     2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) # define LINUX_TIMER_INT XCHAL_TIMER2_INTERRUPT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) # error "Bad timer number for Linux configurations!"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) extern unsigned long ccount_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) typedef unsigned long long cycles_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define get_cycles()	(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) void local_timer_setup(unsigned cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)  * Register access.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) static inline unsigned long get_ccount (void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 	return xtensa_get_sr(ccount);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) static inline void set_ccount (unsigned long ccount)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 	xtensa_set_sr(ccount, ccount);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) static inline unsigned long get_linux_timer (void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 	return xtensa_get_sr(SREG_CCOMPARE + LINUX_TIMER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) static inline void set_linux_timer (unsigned long ccompare)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 	xtensa_set_sr(ccompare, SREG_CCOMPARE + LINUX_TIMER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #endif	/* _XTENSA_TIMEX_H */