^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Copyright (c) 2006 Tensilica, Inc. All Rights Reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * This program is free software; you can redistribute it and/or modify
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * it under the terms of version 2.1 of the GNU Lesser General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * License as published by the Free Software Foundation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * This program is distributed in the hope that it would be useful, but
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * WITHOUT ANY WARRANTY; without even the implied warranty of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * Further, this software is distributed without any warranty that it is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * free of the rightful claim of any third person regarding infringement
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * or the like. Any license provided herein, whether implied or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * otherwise, applies only to this software file. Patent licenses, if
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * any, provided herein do not apply to combinations of this program with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * other software, or any other product whatsoever.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * You should have received a copy of the GNU Lesser General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * License along with this program; if not, write the Free Software
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * Foundation, Inc., 59 Temple Place - Suite 330, Boston MA 02111-1307,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * USA.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #ifndef _XTENSA_REGS_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define _XTENSA_REGS_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) /* Special registers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define SREG_MR 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define SREG_IBREAKENABLE 96
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define SREG_IBREAKA 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define SREG_DBREAKA 144
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define SREG_DBREAKC 160
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define SREG_EPC 176
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define SREG_EPS 192
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define SREG_EXCSAVE 208
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define SREG_CCOMPARE 240
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define SREG_MISC 244
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) /* EXCCAUSE register fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define EXCCAUSE_EXCCAUSE_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define EXCCAUSE_EXCCAUSE_MASK 0x3F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define EXCCAUSE_ILLEGAL_INSTRUCTION 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define EXCCAUSE_SYSTEM_CALL 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define EXCCAUSE_INSTRUCTION_FETCH_ERROR 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define EXCCAUSE_LOAD_STORE_ERROR 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define EXCCAUSE_LEVEL1_INTERRUPT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define EXCCAUSE_ALLOCA 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define EXCCAUSE_INTEGER_DIVIDE_BY_ZERO 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define EXCCAUSE_SPECULATION 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define EXCCAUSE_PRIVILEGED 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define EXCCAUSE_UNALIGNED 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define EXCCAUSE_INSTR_DATA_ERROR 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define EXCCAUSE_LOAD_STORE_DATA_ERROR 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define EXCCAUSE_INSTR_ADDR_ERROR 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define EXCCAUSE_LOAD_STORE_ADDR_ERROR 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define EXCCAUSE_ITLB_MISS 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define EXCCAUSE_ITLB_MULTIHIT 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define EXCCAUSE_ITLB_PRIVILEGE 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define EXCCAUSE_ITLB_SIZE_RESTRICTION 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define EXCCAUSE_FETCH_CACHE_ATTRIBUTE 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define EXCCAUSE_DTLB_MISS 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define EXCCAUSE_DTLB_MULTIHIT 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define EXCCAUSE_DTLB_PRIVILEGE 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define EXCCAUSE_DTLB_SIZE_RESTRICTION 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define EXCCAUSE_LOAD_CACHE_ATTRIBUTE 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define EXCCAUSE_STORE_CACHE_ATTRIBUTE 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define EXCCAUSE_COPROCESSOR0_DISABLED 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define EXCCAUSE_COPROCESSOR1_DISABLED 33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define EXCCAUSE_COPROCESSOR2_DISABLED 34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define EXCCAUSE_COPROCESSOR3_DISABLED 35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define EXCCAUSE_COPROCESSOR4_DISABLED 36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define EXCCAUSE_COPROCESSOR5_DISABLED 37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define EXCCAUSE_COPROCESSOR6_DISABLED 38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define EXCCAUSE_COPROCESSOR7_DISABLED 39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define EXCCAUSE_N 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) /* PS register fields. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define PS_WOE_BIT 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define PS_WOE_MASK 0x00040000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define PS_CALLINC_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define PS_CALLINC_MASK 0x00030000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define PS_OWB_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define PS_OWB_WIDTH 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define PS_OWB_MASK 0x00000F00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define PS_RING_SHIFT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define PS_RING_MASK 0x000000C0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define PS_UM_BIT 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define PS_EXCM_BIT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define PS_INTLEVEL_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define PS_INTLEVEL_WIDTH 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define PS_INTLEVEL_MASK 0x0000000F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) /* DBREAKCn register fields. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define DBREAKC_MASK_BIT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define DBREAKC_MASK_MASK 0x0000003F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define DBREAKC_LOAD_BIT 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define DBREAKC_LOAD_MASK 0x40000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define DBREAKC_STOR_BIT 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define DBREAKC_STOR_MASK 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) /* DEBUGCAUSE register fields. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define DEBUGCAUSE_DBNUM_MASK 0xf00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define DEBUGCAUSE_DBNUM_SHIFT 8 /* First bit of DBNUM field */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define DEBUGCAUSE_DEBUGINT_BIT 5 /* External debug interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define DEBUGCAUSE_BREAKN_BIT 4 /* BREAK.N instruction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define DEBUGCAUSE_BREAK_BIT 3 /* BREAK instruction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define DEBUGCAUSE_DBREAK_BIT 2 /* DBREAK match */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define DEBUGCAUSE_IBREAK_BIT 1 /* IBREAK match */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define DEBUGCAUSE_ICOUNT_BIT 0 /* ICOUNT would incr. to zero */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #endif /* _XTENSA_SPECREG_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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