^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * include/asm-xtensa/pgtable.h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2001 - 2013 Tensilica Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #ifndef _XTENSA_PGTABLE_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define _XTENSA_PGTABLE_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <asm/page.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <asm/kmem_layout.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <asm-generic/pgtable-nopmd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * We only use two ring levels, user and kernel space.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #ifdef CONFIG_MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define USER_RING 1 /* user ring level */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define USER_RING 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define KERNEL_RING 0 /* kernel ring level */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * The Xtensa architecture port of Linux has a two-level page table system,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * i.e. the logical three-level Linux page table layout is folded.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * Each task has the following memory page tables:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * PGD table (page directory), ie. 3rd-level page table:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * One page (4 kB) of 1024 (PTRS_PER_PGD) pointers to PTE tables
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * (Architectures that don't have the PMD folded point to the PMD tables)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * The pointer to the PGD table for a given task can be retrieved from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * the task structure (struct task_struct*) t, e.g. current():
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * (t->mm ? t->mm : t->active_mm)->pgd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * PMD tables (page middle-directory), ie. 2nd-level page tables:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * Absent for the Xtensa architecture (folded, PTRS_PER_PMD == 1).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * PTE tables (page table entry), ie. 1st-level page tables:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * One page (4 kB) of 1024 (PTRS_PER_PTE) PTEs with a special PTE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * invalid_pte_table for absent mappings.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * The individual pages are 4 kB big with special pages for the empty_zero_page.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define PGDIR_SHIFT 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define PGDIR_SIZE (1UL << PGDIR_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define PGDIR_MASK (~(PGDIR_SIZE-1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * Entries per page directory level: we use two-level, so
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * we don't really have any PMD directory physically.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define PTRS_PER_PTE 1024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define PTRS_PER_PTE_SHIFT 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define PTRS_PER_PGD 1024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define PGD_ORDER 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define USER_PTRS_PER_PGD (TASK_SIZE/PGDIR_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define FIRST_USER_ADDRESS 0UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define FIRST_USER_PGD_NR (FIRST_USER_ADDRESS >> PGDIR_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #ifdef CONFIG_MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * Virtual memory area. We keep a distance to other memory regions to be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) * on the safe side. We also use this area for cache aliasing.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define VMALLOC_START (XCHAL_KSEG_CACHED_VADDR - 0x10000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define VMALLOC_END (VMALLOC_START + 0x07FEFFFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define TLBTEMP_BASE_1 (VMALLOC_START + 0x08000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define TLBTEMP_BASE_2 (TLBTEMP_BASE_1 + DCACHE_WAY_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #if 2 * DCACHE_WAY_SIZE > ICACHE_WAY_SIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define TLBTEMP_SIZE (2 * DCACHE_WAY_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define TLBTEMP_SIZE ICACHE_WAY_SIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define VMALLOC_START __XTENSA_UL_CONST(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define VMALLOC_END __XTENSA_UL_CONST(0xffffffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) * For the Xtensa architecture, the PTE layout is as follows:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) * 31------12 11 10-9 8-6 5-4 3-2 1-0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) * +-----------------------------------------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) * | | Software | HARDWARE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) * | PPN | ADW | RI |Attribute|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) * +-----------------------------------------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) * pte_none | MBZ | 01 | 11 | 00 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) * +-----------------------------------------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) * present | PPN | 0 | 00 | ADW | RI | CA | wx |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) * +- - - - - - - - - - - - - - - - - - - - -+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) * (PAGE_NONE)| PPN | 0 | 00 | ADW | 01 | 11 | 11 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) * +-----------------------------------------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) * swap | index | type | 01 | 11 | 00 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) * +-----------------------------------------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) * For T1050 hardware and earlier the layout differs for present and (PAGE_NONE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) * +-----------------------------------------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) * present | PPN | 0 | 00 | ADW | RI | CA | w1 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) * +-----------------------------------------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) * (PAGE_NONE)| PPN | 0 | 00 | ADW | 01 | 01 | 00 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) * +-----------------------------------------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) * Legend:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) * PPN Physical Page Number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) * ADW software: accessed (young) / dirty / writable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) * RI ring (0=privileged, 1=user, 2 and 3 are unused)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) * CA cache attribute: 00 bypass, 01 writeback, 10 writethrough
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) * (11 is invalid and used to mark pages that are not present)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) * w page is writable (hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) * x page is executable (hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) * index swap offset / PAGE_SIZE (bit 11-31: 21 bits -> 8 GB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) * (note that the index is always non-zero)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) * type swap type (5 bits -> 32 types)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) * Notes:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) * - (PROT_NONE) is a special case of 'present' but causes an exception for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) * any access (read, write, and execute).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) * - 'multihit-exception' has the highest priority of all MMU exceptions,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) * so the ring must be set to 'RING_USER' even for 'non-present' pages.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) * - on older hardware, the exectuable flag was not supported and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) * used as a 'valid' flag, so it needs to be always set.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) * - we need to keep track of certain flags in software (dirty and young)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) * to do this, we use write exceptions and have a separate software w-flag.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) * - attribute value 1101 (and 1111 on T1050 and earlier) is reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define _PAGE_ATTRIB_MASK 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define _PAGE_HW_EXEC (1<<0) /* hardware: page is executable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define _PAGE_HW_WRITE (1<<1) /* hardware: page is writable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define _PAGE_CA_BYPASS (0<<2) /* bypass, non-speculative */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define _PAGE_CA_WB (1<<2) /* write-back */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define _PAGE_CA_WT (2<<2) /* write-through */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define _PAGE_CA_MASK (3<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define _PAGE_CA_INVALID (3<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) /* We use invalid attribute values to distinguish special pte entries */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #if XCHAL_HW_VERSION_MAJOR < 2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define _PAGE_HW_VALID 0x01 /* older HW needed this bit set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define _PAGE_NONE 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define _PAGE_HW_VALID 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define _PAGE_NONE 0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define _PAGE_USER (1<<4) /* user access (ring=1) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) /* Software */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define _PAGE_WRITABLE_BIT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define _PAGE_WRITABLE (1<<6) /* software: page writable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define _PAGE_DIRTY (1<<7) /* software: page dirty */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define _PAGE_ACCESSED (1<<8) /* software: page accessed (read) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #ifdef CONFIG_MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_ACCESSED | _PAGE_DIRTY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define _PAGE_PRESENT (_PAGE_HW_VALID | _PAGE_CA_WB | _PAGE_ACCESSED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define PAGE_NONE __pgprot(_PAGE_NONE | _PAGE_USER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define PAGE_COPY __pgprot(_PAGE_PRESENT | _PAGE_USER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define PAGE_COPY_EXEC __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_HW_EXEC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define PAGE_READONLY __pgprot(_PAGE_PRESENT | _PAGE_USER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define PAGE_READONLY_EXEC __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_HW_EXEC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define PAGE_SHARED __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_WRITABLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define PAGE_SHARED_EXEC \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_WRITABLE | _PAGE_HW_EXEC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define PAGE_KERNEL __pgprot(_PAGE_PRESENT | _PAGE_HW_WRITE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define PAGE_KERNEL_RO __pgprot(_PAGE_PRESENT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define PAGE_KERNEL_EXEC __pgprot(_PAGE_PRESENT|_PAGE_HW_WRITE|_PAGE_HW_EXEC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #if (DCACHE_WAY_SIZE > PAGE_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) # define _PAGE_DIRECTORY (_PAGE_HW_VALID | _PAGE_ACCESSED | _PAGE_CA_BYPASS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) # define _PAGE_DIRECTORY (_PAGE_HW_VALID | _PAGE_ACCESSED | _PAGE_CA_WB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #else /* no mmu */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) # define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_ACCESSED | _PAGE_DIRTY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) # define PAGE_NONE __pgprot(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) # define PAGE_SHARED __pgprot(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) # define PAGE_COPY __pgprot(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) # define PAGE_READONLY __pgprot(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) # define PAGE_KERNEL __pgprot(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) * On certain configurations of Xtensa MMUs (eg. the initial Linux config),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) * the MMU can't do page protection for execute, and considers that the same as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) * read. Also, write permissions may imply read permissions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) * What follows is the closest we can get by reasonable means..
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) * See linux/mm/mmap.c for protection_map[] array that uses these definitions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define __P000 PAGE_NONE /* private --- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define __P001 PAGE_READONLY /* private --r */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define __P010 PAGE_COPY /* private -w- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define __P011 PAGE_COPY /* private -wr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define __P100 PAGE_READONLY_EXEC /* private x-- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define __P101 PAGE_READONLY_EXEC /* private x-r */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define __P110 PAGE_COPY_EXEC /* private xw- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define __P111 PAGE_COPY_EXEC /* private xwr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define __S000 PAGE_NONE /* shared --- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define __S001 PAGE_READONLY /* shared --r */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define __S010 PAGE_SHARED /* shared -w- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define __S011 PAGE_SHARED /* shared -wr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define __S100 PAGE_READONLY_EXEC /* shared x-- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define __S101 PAGE_READONLY_EXEC /* shared x-r */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define __S110 PAGE_SHARED_EXEC /* shared xw- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define __S111 PAGE_SHARED_EXEC /* shared xwr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #ifndef __ASSEMBLY__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define pte_ERROR(e) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) printk("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define pgd_ERROR(e) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) printk("%s:%d: bad pgd entry %08lx.\n", __FILE__, __LINE__, pgd_val(e))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) extern unsigned long empty_zero_page[1024];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #ifdef CONFIG_MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) extern pgd_t swapper_pg_dir[PAGE_SIZE/sizeof(pgd_t)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) extern void paging_init(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) # define swapper_pg_dir NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) static inline void paging_init(void) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) * The pmd contains the kernel virtual address of the pte page.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define pmd_page_vaddr(pmd) ((unsigned long)(pmd_val(pmd) & PAGE_MASK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define pmd_page(pmd) virt_to_page(pmd_val(pmd))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) * pte status.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) # define pte_none(pte) (pte_val(pte) == (_PAGE_CA_INVALID | _PAGE_USER))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #if XCHAL_HW_VERSION_MAJOR < 2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) # define pte_present(pte) ((pte_val(pte) & _PAGE_CA_MASK) != _PAGE_CA_INVALID)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) # define pte_present(pte) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) (((pte_val(pte) & _PAGE_CA_MASK) != _PAGE_CA_INVALID) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) || ((pte_val(pte) & _PAGE_ATTRIB_MASK) == _PAGE_NONE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define pte_clear(mm,addr,ptep) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) do { update_pte(ptep, __pte(_PAGE_CA_INVALID | _PAGE_USER)); } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define pmd_none(pmd) (!pmd_val(pmd))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define pmd_present(pmd) (pmd_val(pmd) & PAGE_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define pmd_bad(pmd) (pmd_val(pmd) & ~PAGE_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define pmd_clear(pmdp) do { set_pmd(pmdp, __pmd(0)); } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) static inline int pte_write(pte_t pte) { return pte_val(pte) & _PAGE_WRITABLE; }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) static inline int pte_dirty(pte_t pte) { return pte_val(pte) & _PAGE_DIRTY; }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) static inline int pte_young(pte_t pte) { return pte_val(pte) & _PAGE_ACCESSED; }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) static inline pte_t pte_wrprotect(pte_t pte)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) { pte_val(pte) &= ~(_PAGE_WRITABLE | _PAGE_HW_WRITE); return pte; }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) static inline pte_t pte_mkclean(pte_t pte)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) { pte_val(pte) &= ~(_PAGE_DIRTY | _PAGE_HW_WRITE); return pte; }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) static inline pte_t pte_mkold(pte_t pte)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) { pte_val(pte) &= ~_PAGE_ACCESSED; return pte; }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) static inline pte_t pte_mkdirty(pte_t pte)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) { pte_val(pte) |= _PAGE_DIRTY; return pte; }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) static inline pte_t pte_mkyoung(pte_t pte)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) { pte_val(pte) |= _PAGE_ACCESSED; return pte; }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) static inline pte_t pte_mkwrite(pte_t pte)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) { pte_val(pte) |= _PAGE_WRITABLE; return pte; }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define pgprot_noncached(prot) (__pgprot(pgprot_val(prot) & ~_PAGE_CA_MASK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) * Conversion functions: convert a page and protection to a page entry,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) * and a page entry and page directory to the page they refer to.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define pte_pfn(pte) (pte_val(pte) >> PAGE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define pte_same(a,b) (pte_val(a) == pte_val(b))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define pte_page(x) pfn_to_page(pte_pfn(x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define pfn_pte(pfn, prot) __pte(((pfn) << PAGE_SHIFT) | pgprot_val(prot))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define mk_pte(page, prot) pfn_pte(page_to_pfn(page), prot)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) return __pte((pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) * Certain architectures need to do special things when pte's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) * within a page table are directly modified. Thus, the following
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) * hook is made available.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) static inline void update_pte(pte_t *ptep, pte_t pteval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) *ptep = pteval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #if (DCACHE_WAY_SIZE > PAGE_SIZE) && XCHAL_DCACHE_IS_WRITEBACK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) __asm__ __volatile__ ("dhwb %0, 0" :: "a" (ptep));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) struct mm_struct;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) set_pte_at(struct mm_struct *mm, unsigned long addr, pte_t *ptep, pte_t pteval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) update_pte(ptep, pteval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) static inline void set_pte(pte_t *ptep, pte_t pteval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) update_pte(ptep, pteval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) set_pmd(pmd_t *pmdp, pmd_t pmdval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) *pmdp = pmdval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) struct vm_area_struct;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) static inline int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) ptep_test_and_clear_young(struct vm_area_struct *vma, unsigned long addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) pte_t *ptep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) pte_t pte = *ptep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) if (!pte_young(pte))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) update_pte(ptep, pte_mkold(pte));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) static inline pte_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) ptep_get_and_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) pte_t pte = *ptep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) pte_clear(mm, addr, ptep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) return pte;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) pte_t pte = *ptep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) update_pte(ptep, pte_wrprotect(pte));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) * Encode and decode a swap and file entry.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) #define SWP_TYPE_BITS 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) #define MAX_SWAPFILES_CHECK() BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > SWP_TYPE_BITS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) #define __swp_type(entry) (((entry).val >> 6) & 0x1f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) #define __swp_offset(entry) ((entry).val >> 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) #define __swp_entry(type,offs) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) ((swp_entry_t){((type) << 6) | ((offs) << 11) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) _PAGE_CA_INVALID | _PAGE_USER})
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) #define __swp_entry_to_pte(x) ((pte_t) { (x).val })
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) #endif /* !defined (__ASSEMBLY__) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) #ifdef __ASSEMBLY__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) /* Assembly macro _PGD_INDEX is the same as C pgd_index(unsigned long),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) * _PGD_OFFSET as C pgd_offset(struct mm_struct*, unsigned long),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) * _PMD_OFFSET as C pmd_offset(pgd_t*, unsigned long)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) * _PTE_OFFSET as C pte_offset(pmd_t*, unsigned long)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) * Note: We require an additional temporary register which can be the same as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) * the register that holds the address.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) * ((pte_t*) ((unsigned long)(pmd_val(*pmd) & PAGE_MASK)) + pte_index(addr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) #define _PGD_INDEX(rt,rs) extui rt, rs, PGDIR_SHIFT, 32-PGDIR_SHIFT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) #define _PTE_INDEX(rt,rs) extui rt, rs, PAGE_SHIFT, PTRS_PER_PTE_SHIFT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) #define _PGD_OFFSET(mm,adr,tmp) l32i mm, mm, MM_PGD; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) _PGD_INDEX(tmp, adr); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) addx4 mm, tmp, mm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) #define _PTE_OFFSET(pmd,adr,tmp) _PTE_INDEX(tmp, adr); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) srli pmd, pmd, PAGE_SHIFT; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) slli pmd, pmd, PAGE_SHIFT; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) addx4 pmd, tmp, pmd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) #define kern_addr_valid(addr) (1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) extern void update_mmu_cache(struct vm_area_struct * vma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) unsigned long address, pte_t *ptep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) typedef pte_t *pte_addr_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) #endif /* !defined (__ASSEMBLY__) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) #define __HAVE_ARCH_PTEP_GET_AND_CLEAR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) #define __HAVE_ARCH_PTEP_SET_WRPROTECT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) #define __HAVE_ARCH_PTEP_MKDIRTY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) #define __HAVE_ARCH_PTE_SAME
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) /* We provide our own get_unmapped_area to cope with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) * SHM area cache aliasing for userland.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) #define HAVE_ARCH_UNMAPPED_AREA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) #endif /* _XTENSA_PGTABLE_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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