Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2)  * Xtensa MX interrupt distributor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  * This file is subject to the terms and conditions of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * License.  See the file "COPYING" in the main directory of this archive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  * for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)  * Copyright (C) 2008 - 2013 Tensilica Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #ifndef _XTENSA_MXREGS_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define _XTENSA_MXREGS_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)  * RER/WER at, as	Read/write external register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)  *	at: value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)  *	as: address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)  * Address	Value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)  * 00nn		0...0p..p	Interrupt Routing, route IRQ n to processor p
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)  * 01pp		0...0d..d	16 bits (d) 'ored' as single IPI to processor p
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)  * 0180		0...0m..m	Clear enable specified by mask (m)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)  * 0184		0...0m..m	Set enable specified by mask (m)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)  * 0190		0...0x..x	8-bit IPI partition register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)  *				VVVVVVVVPPPPUUUUUUUUUUUUUUUUU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)  *				V (10-bit) Release/Version
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)  *				P ( 4-bit) Number of cores - 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)  *				U (18-bit) ID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)  * 01a0		i.......i	32-bit ConfigID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)  * 0200		0...0m..m	RunStall core 'n'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)  * 0220		c		Cache coherency enabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define MIROUT(irq)	(0x000 + (irq))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define MIPICAUSE(cpu)	(0x100 + (cpu))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define MIPISET(cause)	(0x140 + (cause))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define MIENG		0x180
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define MIENGSET	0x184
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define MIASG		0x188	/* Read Global Assert Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define MIASGSET	0x18c	/* Set Global Addert Regiter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define MIPIPART	0x190
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define SYSCFGID	0x1a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define MPSCORE		0x200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define CCON		0x220
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #endif /* _XTENSA_MXREGS_H */