Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2)  * include/asm-xtensa/io.h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  * This file is subject to the terms and conditions of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * License.  See the file "COPYING" in the main directory of this archive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  * for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)  * Copyright (C) 2001 - 2005 Tensilica Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #ifndef _XTENSA_IO_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define _XTENSA_IO_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <asm/byteorder.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <asm/page.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <asm/vectors.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/bug.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define IOADDR(x)		(XCHAL_KIO_BYPASS_VADDR + (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define IO_SPACE_LIMIT ~0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define PCI_IOBASE		((void __iomem *)XCHAL_KIO_BYPASS_VADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #ifdef CONFIG_MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) void __iomem *xtensa_ioremap_nocache(unsigned long addr, unsigned long size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) void __iomem *xtensa_ioremap_cache(unsigned long addr, unsigned long size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) void xtensa_iounmap(volatile void __iomem *addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)  * Return the virtual address for the specified bus memory.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) static inline void __iomem *ioremap(unsigned long offset, unsigned long size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 	if (offset >= XCHAL_KIO_PADDR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 	    && offset - XCHAL_KIO_PADDR < XCHAL_KIO_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 		return (void*)(offset-XCHAL_KIO_PADDR+XCHAL_KIO_BYPASS_VADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 		return xtensa_ioremap_nocache(offset, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) static inline void __iomem *ioremap_cache(unsigned long offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 		unsigned long size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 	if (offset >= XCHAL_KIO_PADDR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 	    && offset - XCHAL_KIO_PADDR < XCHAL_KIO_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 		return (void*)(offset-XCHAL_KIO_PADDR+XCHAL_KIO_CACHED_VADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 		return xtensa_ioremap_cache(offset, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define ioremap_cache ioremap_cache
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) static inline void iounmap(volatile void __iomem *addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 	unsigned long va = (unsigned long) addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 	if (!(va >= XCHAL_KIO_CACHED_VADDR &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 	      va - XCHAL_KIO_CACHED_VADDR < XCHAL_KIO_SIZE) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 	    !(va >= XCHAL_KIO_BYPASS_VADDR &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 	      va - XCHAL_KIO_BYPASS_VADDR < XCHAL_KIO_SIZE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 		xtensa_iounmap(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define virt_to_bus     virt_to_phys
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define bus_to_virt     phys_to_virt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #endif /* CONFIG_MMU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #include <asm-generic/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #endif	/* _XTENSA_IO_H */