^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Atomic futex routines
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Based on the PowerPC implementataion
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) 2013 TangoTec Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Baruch Siach <baruch@tkos.co.il>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #ifndef _ASM_XTENSA_FUTEX_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define _ASM_XTENSA_FUTEX_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/futex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/uaccess.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #if XCHAL_HAVE_EXCLUSIVE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define __futex_atomic_op(insn, ret, old, uaddr, arg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) __asm__ __volatile( \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) "1: l32ex %[oldval], %[addr]\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) insn "\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) "2: s32ex %[newval], %[addr]\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) " getex %[newval]\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) " beqz %[newval], 1b\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) " movi %[newval], 0\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) "3:\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) " .section .fixup,\"ax\"\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) " .align 4\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) " .literal_position\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) "5: movi %[oldval], 3b\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) " movi %[newval], %[fault]\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) " jx %[oldval]\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) " .previous\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) " .section __ex_table,\"a\"\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) " .long 1b, 5b, 2b, 5b\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) " .previous\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) : [oldval] "=&r" (old), [newval] "=&r" (ret) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) : [addr] "r" (uaddr), [oparg] "r" (arg), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) [fault] "I" (-EFAULT) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) : "memory")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #elif XCHAL_HAVE_S32C1I
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define __futex_atomic_op(insn, ret, old, uaddr, arg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) __asm__ __volatile( \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) "1: l32i %[oldval], %[mem]\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) insn "\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) " wsr %[oldval], scompare1\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) "2: s32c1i %[newval], %[mem]\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) " bne %[newval], %[oldval], 1b\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) " movi %[newval], 0\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) "3:\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) " .section .fixup,\"ax\"\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) " .align 4\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) " .literal_position\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) "5: movi %[oldval], 3b\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) " movi %[newval], %[fault]\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) " jx %[oldval]\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) " .previous\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) " .section __ex_table,\"a\"\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) " .long 1b, 5b, 2b, 5b\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) " .previous\n" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) : [oldval] "=&r" (old), [newval] "=&r" (ret), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) [mem] "+m" (*(uaddr)) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) : [oparg] "r" (arg), [fault] "I" (-EFAULT) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) : "memory")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) static inline int arch_futex_atomic_op_inuser(int op, int oparg, int *oval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) u32 __user *uaddr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #if XCHAL_HAVE_S32C1I || XCHAL_HAVE_EXCLUSIVE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) int oldval = 0, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) if (!access_ok(uaddr, sizeof(u32)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) switch (op) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) case FUTEX_OP_SET:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) __futex_atomic_op("mov %[newval], %[oparg]",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) ret, oldval, uaddr, oparg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) case FUTEX_OP_ADD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) __futex_atomic_op("add %[newval], %[oldval], %[oparg]",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) ret, oldval, uaddr, oparg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) case FUTEX_OP_OR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) __futex_atomic_op("or %[newval], %[oldval], %[oparg]",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) ret, oldval, uaddr, oparg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) case FUTEX_OP_ANDN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) __futex_atomic_op("and %[newval], %[oldval], %[oparg]",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) ret, oldval, uaddr, ~oparg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) case FUTEX_OP_XOR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) __futex_atomic_op("xor %[newval], %[oldval], %[oparg]",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) ret, oldval, uaddr, oparg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) ret = -ENOSYS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) *oval = oldval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) return -ENOSYS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) static inline int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) u32 oldval, u32 newval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #if XCHAL_HAVE_S32C1I || XCHAL_HAVE_EXCLUSIVE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) unsigned long tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) if (!access_ok(uaddr, sizeof(u32)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) __asm__ __volatile__ (
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) " # futex_atomic_cmpxchg_inatomic\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #if XCHAL_HAVE_EXCLUSIVE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) "1: l32ex %[tmp], %[addr]\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) " s32i %[tmp], %[uval], 0\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) " bne %[tmp], %[oldval], 2f\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) " mov %[tmp], %[newval]\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) "3: s32ex %[tmp], %[addr]\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) " getex %[tmp]\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) " beqz %[tmp], 1b\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #elif XCHAL_HAVE_S32C1I
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) " wsr %[oldval], scompare1\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) "1: s32c1i %[newval], %[addr], 0\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) " s32i %[newval], %[uval], 0\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) "2:\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) " .section .fixup,\"ax\"\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) " .align 4\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) " .literal_position\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) "4: movi %[tmp], 2b\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) " movi %[ret], %[fault]\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) " jx %[tmp]\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) " .previous\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) " .section __ex_table,\"a\"\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) " .long 1b, 4b\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #if XCHAL_HAVE_EXCLUSIVE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) " .long 3b, 4b\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) " .previous\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) : [ret] "+r" (ret), [newval] "+r" (newval), [tmp] "=&r" (tmp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) : [addr] "r" (uaddr), [oldval] "r" (oldval), [uval] "r" (uval),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) [fault] "I" (-EFAULT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) : "memory");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) return -ENOSYS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #endif /* _ASM_XTENSA_FUTEX_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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