^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * include/asm-xtensa/elf.h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * ELF register definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * This file is subject to the terms and conditions of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * License. See the file "COPYING" in the main directory of this archive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Copyright (C) 2001 - 2005 Tensilica Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #ifndef _XTENSA_ELF_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define _XTENSA_ELF_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <asm/ptrace.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <asm/coprocessor.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/elf-em.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) /* Xtensa processor ELF architecture-magic number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define EM_XTENSA_OLD 0xABC7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) /* Xtensa relocations defined by the ABIs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define R_XTENSA_NONE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define R_XTENSA_32 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define R_XTENSA_RTLD 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define R_XTENSA_GLOB_DAT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define R_XTENSA_JMP_SLOT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define R_XTENSA_RELATIVE 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define R_XTENSA_PLT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define R_XTENSA_OP0 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define R_XTENSA_OP1 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define R_XTENSA_OP2 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define R_XTENSA_ASM_EXPAND 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define R_XTENSA_ASM_SIMPLIFY 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define R_XTENSA_GNU_VTINHERIT 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define R_XTENSA_GNU_VTENTRY 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define R_XTENSA_DIFF8 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define R_XTENSA_DIFF16 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define R_XTENSA_DIFF32 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define R_XTENSA_SLOT0_OP 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define R_XTENSA_SLOT1_OP 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define R_XTENSA_SLOT2_OP 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define R_XTENSA_SLOT3_OP 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define R_XTENSA_SLOT4_OP 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define R_XTENSA_SLOT5_OP 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define R_XTENSA_SLOT6_OP 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define R_XTENSA_SLOT7_OP 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define R_XTENSA_SLOT8_OP 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define R_XTENSA_SLOT9_OP 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define R_XTENSA_SLOT10_OP 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define R_XTENSA_SLOT11_OP 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define R_XTENSA_SLOT12_OP 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define R_XTENSA_SLOT13_OP 33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define R_XTENSA_SLOT14_OP 34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define R_XTENSA_SLOT0_ALT 35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define R_XTENSA_SLOT1_ALT 36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define R_XTENSA_SLOT2_ALT 37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define R_XTENSA_SLOT3_ALT 38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define R_XTENSA_SLOT4_ALT 39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define R_XTENSA_SLOT5_ALT 40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define R_XTENSA_SLOT6_ALT 41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define R_XTENSA_SLOT7_ALT 42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define R_XTENSA_SLOT8_ALT 43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define R_XTENSA_SLOT9_ALT 44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define R_XTENSA_SLOT10_ALT 45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define R_XTENSA_SLOT11_ALT 46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define R_XTENSA_SLOT12_ALT 47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define R_XTENSA_SLOT13_ALT 48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define R_XTENSA_SLOT14_ALT 49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) /* ELF register definitions. This is needed for core dump support. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) typedef unsigned long elf_greg_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) typedef struct user_pt_regs xtensa_gregset_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define ELF_NGREG (sizeof(xtensa_gregset_t) / sizeof(elf_greg_t))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) typedef elf_greg_t elf_gregset_t[ELF_NGREG];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define ELF_NFPREG 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) typedef unsigned int elf_fpreg_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) typedef elf_fpreg_t elf_fpregset_t[ELF_NFPREG];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) * This is used to ensure we don't load something for the wrong architecture.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define elf_check_arch(x) ( ( (x)->e_machine == EM_XTENSA ) || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) ( (x)->e_machine == EM_XTENSA_OLD ) )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) * These are used to set parameters in the core dumps.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #ifdef __XTENSA_EL__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) # define ELF_DATA ELFDATA2LSB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #elif defined(__XTENSA_EB__)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) # define ELF_DATA ELFDATA2MSB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) # error processor byte order undefined!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define ELF_CLASS ELFCLASS32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define ELF_ARCH EM_XTENSA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define ELF_EXEC_PAGESIZE PAGE_SIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define CORE_DUMP_USE_REGSET
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) * This is the location that an ET_DYN program is loaded if exec'ed. Typical
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) * use of this is to invoke "./ld.so someprog" to test out a new version of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) * the loader. We need to make sure that it is out of the way of the program
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) * that it will "exec", and that there is sufficient room for the brk.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define ELF_ET_DYN_BASE (2 * TASK_SIZE / 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) * This yields a mask that user programs can use to figure out what
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) * instruction set this CPU supports. This could be done in user space,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) * but it's not easy, and we've already done it here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define ELF_HWCAP (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) * This yields a string that ld.so will use to load implementation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) * specific libraries for optimization. This is more specific in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) * intent than poking at uname or /proc/cpuinfo.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) * For the moment, we have only optimizations for the Intel generations,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) * but that could change...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define ELF_PLATFORM (NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) * The Xtensa processor ABI says that when the program starts, a2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) * contains a pointer to a function which might be registered using
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) * `atexit'. This provides a mean for the dynamic linker to call
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) * DT_FINI functions for shared libraries that have been loaded before
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) * the code runs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) * A value of 0 tells we have no such handler.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) * We might as well make sure everything else is cleared too (except
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) * for the stack pointer in a1), just to make things more
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) * deterministic. Also, clearing a0 terminates debugger backtraces.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define ELF_PLAT_INIT(_r, load_addr) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) do { _r->areg[0]=0; /*_r->areg[1]=0;*/ _r->areg[2]=0; _r->areg[3]=0; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) _r->areg[4]=0; _r->areg[5]=0; _r->areg[6]=0; _r->areg[7]=0; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) _r->areg[8]=0; _r->areg[9]=0; _r->areg[10]=0; _r->areg[11]=0; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) _r->areg[12]=0; _r->areg[13]=0; _r->areg[14]=0; _r->areg[15]=0; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) xtregs_opt_t opt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) xtregs_user_t user;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #if XTENSA_HAVE_COPROCESSORS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) xtregs_cp0_t cp0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) xtregs_cp1_t cp1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) xtregs_cp2_t cp2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) xtregs_cp3_t cp3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) xtregs_cp4_t cp4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) xtregs_cp5_t cp5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) xtregs_cp6_t cp6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) xtregs_cp7_t cp7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) } elf_xtregs_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define SET_PERSONALITY(ex) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) set_personality(PER_LINUX_32BIT | (current->personality & (~PER_MASK)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #endif /* _XTENSA_ELF_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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