Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2)  * include/asm-xtensa/dma.h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  * This file is subject to the terms and conditions of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * License.  See the file "COPYING" in the main directory of this archive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  * for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)  * Copyright (C) 2003 - 2005 Tensilica Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #ifndef _XTENSA_DMA_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define _XTENSA_DMA_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <asm/io.h>		/* need byte IO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)  * This is only to be defined if we have PC-like DMA.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)  * By default this is not true on an Xtensa processor,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)  * however on boards with a PCI bus, such functionality
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)  * might be emulated externally.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)  * NOTE:  there still exists driver code that assumes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)  * this is defined, eg. drivers/sound/soundcard.c (as of 2.4).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define MAX_DMA_CHANNELS	8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)  * The maximum virtual address to which DMA transfers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)  * can be performed on this platform.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)  * NOTE: This is board (platform) specific, not processor-specific!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)  * NOTE: This assumes DMA transfers can only be performed on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)  *	the section of physical memory contiguously mapped in virtual
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)  *	space for the kernel.  For the Xtensa architecture, this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)  *	means the maximum possible size of this DMA area is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)  *	the size of the statically mapped kernel segment
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)  *	(XCHAL_KSEG_{CACHED,BYPASS}_SIZE), ie. 128 MB.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)  * NOTE: When the entire KSEG area is DMA capable, we subtract
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)  *	one from the max address so that the virt_to_phys() macro
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)  *	works correctly on the address (otherwise the address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)  *	enters another area, and virt_to_phys() may not return
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)  *	the value desired).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #ifndef MAX_DMA_ADDRESS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define MAX_DMA_ADDRESS		(PAGE_OFFSET + XCHAL_KIO_SIZE - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) /* Reserve and release a DMA channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) extern int request_dma(unsigned int dmanr, const char * device_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) extern void free_dma(unsigned int dmanr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #ifdef CONFIG_PCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) extern int isa_dma_bridge_buggy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define isa_dma_bridge_buggy 	(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #endif