^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * include/asm-xtensa/cacheasm.h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * This file is subject to the terms and conditions of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * License. See the file "COPYING" in the main directory of this archive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Copyright (C) 2006 Tensilica Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <asm/cache.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <asm/asmmacro.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/stringify.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * Define cache functions as macros here so that they can be used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * by the kernel and boot loader. We should consider moving them to a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * library that can be linked by both.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * Locking
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * ___unlock_dcache_all
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * ___unlock_icache_all
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * Flush and invaldating
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * ___flush_invalidate_dcache_{all|range|page}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * ___flush_dcache_{all|range|page}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * ___invalidate_dcache_{all|range|page}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * ___invalidate_icache_{all|range|page}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) .macro __loop_cache_unroll ar at insn size line_width max_immed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) .if (1 << (\line_width)) > (\max_immed)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) .set _reps, 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) .elseif (2 << (\line_width)) > (\max_immed)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) .set _reps, 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) .else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) .set _reps, 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) .endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) __loopi \ar, \at, \size, (_reps << (\line_width))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) .set _index, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) .rep _reps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) \insn \ar, _index << (\line_width)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) .set _index, _index + 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) .endr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) __endla \ar, \at, _reps << (\line_width)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) .endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) .macro __loop_cache_all ar at insn size line_width max_immed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) movi \ar, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) __loop_cache_unroll \ar, \at, \insn, \size, \line_width, \max_immed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) .endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) .macro __loop_cache_range ar as at insn line_width
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) extui \at, \ar, 0, \line_width
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) add \as, \as, \at
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) __loops \ar, \as, \at, \line_width
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) \insn \ar, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) __endla \ar, \at, (1 << (\line_width))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) .endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) .macro __loop_cache_page ar at insn line_width max_immed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) __loop_cache_unroll \ar, \at, \insn, PAGE_SIZE, \line_width, \max_immed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) .endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) .macro ___unlock_dcache_all ar at
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #if XCHAL_DCACHE_LINE_LOCKABLE && XCHAL_DCACHE_SIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) __loop_cache_all \ar \at diu XCHAL_DCACHE_SIZE \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) XCHAL_DCACHE_LINEWIDTH 240
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) .endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) .macro ___unlock_icache_all ar at
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #if XCHAL_ICACHE_LINE_LOCKABLE && XCHAL_ICACHE_SIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) __loop_cache_all \ar \at iiu XCHAL_ICACHE_SIZE \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) XCHAL_ICACHE_LINEWIDTH 240
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) .endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) .macro ___flush_invalidate_dcache_all ar at
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #if XCHAL_DCACHE_SIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) __loop_cache_all \ar \at diwbi XCHAL_DCACHE_SIZE \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) XCHAL_DCACHE_LINEWIDTH 240
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) .endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) .macro ___flush_dcache_all ar at
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #if XCHAL_DCACHE_SIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) __loop_cache_all \ar \at diwb XCHAL_DCACHE_SIZE \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) XCHAL_DCACHE_LINEWIDTH 240
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) .endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) .macro ___invalidate_dcache_all ar at
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #if XCHAL_DCACHE_SIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) __loop_cache_all \ar \at dii XCHAL_DCACHE_SIZE \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) XCHAL_DCACHE_LINEWIDTH 1020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) .endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) .macro ___invalidate_icache_all ar at
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #if XCHAL_ICACHE_SIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) __loop_cache_all \ar \at iii XCHAL_ICACHE_SIZE \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) XCHAL_ICACHE_LINEWIDTH 1020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) .endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) .macro ___flush_invalidate_dcache_range ar as at
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #if XCHAL_DCACHE_SIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) __loop_cache_range \ar \as \at dhwbi XCHAL_DCACHE_LINEWIDTH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) .endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) .macro ___flush_dcache_range ar as at
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #if XCHAL_DCACHE_SIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) __loop_cache_range \ar \as \at dhwb XCHAL_DCACHE_LINEWIDTH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) .endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) .macro ___invalidate_dcache_range ar as at
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #if XCHAL_DCACHE_SIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) __loop_cache_range \ar \as \at dhi XCHAL_DCACHE_LINEWIDTH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) .endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) .macro ___invalidate_icache_range ar as at
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #if XCHAL_ICACHE_SIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) __loop_cache_range \ar \as \at ihi XCHAL_ICACHE_LINEWIDTH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) .endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) .macro ___flush_invalidate_dcache_page ar as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #if XCHAL_DCACHE_SIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) __loop_cache_page \ar \as dhwbi XCHAL_DCACHE_LINEWIDTH 1020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) .endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) .macro ___flush_dcache_page ar as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #if XCHAL_DCACHE_SIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) __loop_cache_page \ar \as dhwb XCHAL_DCACHE_LINEWIDTH 1020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) .endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) .macro ___invalidate_dcache_page ar as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #if XCHAL_DCACHE_SIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) __loop_cache_page \ar \as dhi XCHAL_DCACHE_LINEWIDTH 1020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) .endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) .macro ___invalidate_icache_page ar as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #if XCHAL_ICACHE_SIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) __loop_cache_page \ar \as ihi XCHAL_ICACHE_LINEWIDTH 1020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) .endm
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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