Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2)  * include/asm-xtensa/cache.h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  * This file is subject to the terms and conditions of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * License.  See the file "COPYING" in the main directory of this archive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  * for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)  * (C) 2001 - 2005 Tensilica Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #ifndef _XTENSA_CACHE_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define _XTENSA_CACHE_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <asm/core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define L1_CACHE_SHIFT	XCHAL_DCACHE_LINEWIDTH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define L1_CACHE_BYTES	XCHAL_DCACHE_LINESIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define SMP_CACHE_BYTES	L1_CACHE_BYTES
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define DCACHE_WAY_SIZE	(XCHAL_DCACHE_SIZE/XCHAL_DCACHE_WAYS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define ICACHE_WAY_SIZE	(XCHAL_ICACHE_SIZE/XCHAL_ICACHE_WAYS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define DCACHE_WAY_SHIFT (XCHAL_DCACHE_SETWIDTH + XCHAL_DCACHE_LINEWIDTH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define ICACHE_WAY_SHIFT (XCHAL_ICACHE_SETWIDTH + XCHAL_ICACHE_LINEWIDTH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) /* Maximum cache size per way. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #if DCACHE_WAY_SIZE >= ICACHE_WAY_SIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) # define CACHE_WAY_SIZE DCACHE_WAY_SIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) # define CACHE_WAY_SIZE ICACHE_WAY_SIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define ARCH_DMA_MINALIGN	L1_CACHE_BYTES
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)  * R/O after init is actually writable, it cannot go to .rodata
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)  * according to vmlinux linker script.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define __ro_after_init __read_mostly
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #endif	/* _XTENSA_CACHE_H */