^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * include/asm-xtensa/asmmacro.h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * This file is subject to the terms and conditions of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * License. See the file "COPYING" in the main directory of this archive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Copyright (C) 2005 Tensilica Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #ifndef _XTENSA_ASMMACRO_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define _XTENSA_ASMMACRO_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <asm/core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * Some little helpers for loops. Use zero-overhead-loops
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * where applicable and if supported by the processor.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * __loopi ar, at, size, inc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * ar register initialized with the start address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * at scratch register used by macro
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * size size immediate value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * inc increment
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * __loops ar, as, at, inc_log2[, mask_log2][, cond][, ncond]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * ar register initialized with the start address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * as register initialized with the size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * at scratch register use by macro
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * inc_log2 increment [in log2]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * mask_log2 mask [in log2]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * cond true condition (used in loop'cond')
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * ncond false condition (used in b'ncond')
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * __loop as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * restart loop. 'as' register must not have been modified!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * __endla ar, as, incr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * ar start address (modified)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * as scratch register used by __loops/__loopi macros or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * end address used by __loopt macro
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * inc increment
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * loop for given size as immediate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) .macro __loopi ar, at, size, incr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #if XCHAL_HAVE_LOOPS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) movi \at, ((\size + \incr - 1) / (\incr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) loop \at, 99f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) addi \at, \ar, \size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 98:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) .endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * loop for given size in register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) .macro __loops ar, as, at, incr_log2, mask_log2, cond, ncond
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #if XCHAL_HAVE_LOOPS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) .ifgt \incr_log2 - 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) addi \at, \as, (1 << \incr_log2) - 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) .ifnc \mask_log2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) extui \at, \at, \incr_log2, \mask_log2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) .else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) srli \at, \at, \incr_log2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) .endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) .endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) loop\cond \at, 99f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) .ifnc \mask_log2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) extui \at, \as, \incr_log2, \mask_log2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) .else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) .ifnc \ncond,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) srli \at, \as, \incr_log2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) .endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) .endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) .ifnc \ncond,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) b\ncond \at, 99f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) .endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) .ifnc \mask_log2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) slli \at, \at, \incr_log2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) add \at, \ar, \at
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) .else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) add \at, \ar, \as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) .endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) 98:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) .endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) * loop from ar to as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) .macro __loopt ar, as, at, incr_log2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #if XCHAL_HAVE_LOOPS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) sub \at, \as, \ar
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) .ifgt \incr_log2 - 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) addi \at, \at, (1 << \incr_log2) - 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) srli \at, \at, \incr_log2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) .endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) loop \at, 99f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 98:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) .endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) * restart loop. registers must be unchanged
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) .macro __loop as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #if XCHAL_HAVE_LOOPS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) loop \as, 99f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 98:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) .endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) * end of loop with no increment of the address.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) .macro __endl ar, as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #if !XCHAL_HAVE_LOOPS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) bltu \ar, \as, 98b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 99:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) .endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) * end of loop with increment of the address.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) .macro __endla ar, as, incr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) addi \ar, \ar, \incr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) __endl \ar \as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) .endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) /* Load or store instructions that may cause exceptions use the EX macro. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define EX(handler) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) .section __ex_table, "a"; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) .word 97f, handler; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) .previous \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 97:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) * Extract unaligned word that is split between two registers w0 and w1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) * into r regardless of machine endianness. SAR must be loaded with the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) * starting bit of the word (see __ssa8).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) .macro __src_b r, w0, w1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #ifdef __XTENSA_EB__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) src \r, \w0, \w1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) src \r, \w1, \w0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) .endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) * Load 2 lowest address bits of r into SAR for __src_b to extract unaligned
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) * word starting at r from two registers loaded from consecutive aligned
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) * addresses covering r regardless of machine endianness.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) * r 0 1 2 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) * LE SAR 0 8 16 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) * BE SAR 32 24 16 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) .macro __ssa8 r
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #ifdef __XTENSA_EB__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) ssa8b \r
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) ssa8l \r
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) .endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define XTENSA_STACK_ALIGNMENT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #if defined(__XTENSA_WINDOWED_ABI__)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define XTENSA_FRAME_SIZE_RESERVE 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define XTENSA_SPILL_STACK_RESERVE 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define abi_entry(frame_size) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) entry sp, (XTENSA_FRAME_SIZE_RESERVE + \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) (((frame_size) + XTENSA_STACK_ALIGNMENT - 1) & \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) -XTENSA_STACK_ALIGNMENT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define abi_entry_default abi_entry(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define abi_ret(frame_size) retw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define abi_ret_default retw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #elif defined(__XTENSA_CALL0_ABI__)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define XTENSA_SPILL_STACK_RESERVE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define abi_entry(frame_size) __abi_entry (frame_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) .macro __abi_entry frame_size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) .ifgt \frame_size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) addi sp, sp, -(((\frame_size) + XTENSA_STACK_ALIGNMENT - 1) & \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) -XTENSA_STACK_ALIGNMENT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) .endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) .endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define abi_entry_default
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define abi_ret(frame_size) __abi_ret (frame_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) .macro __abi_ret frame_size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) .ifgt \frame_size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) addi sp, sp, (((\frame_size) + XTENSA_STACK_ALIGNMENT - 1) & \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) -XTENSA_STACK_ALIGNMENT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) .endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) ret
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) .endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define abi_ret_default ret
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #error Unsupported Xtensa ABI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define __XTENSA_HANDLER .section ".exception.text", "ax"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #endif /* _XTENSA_ASMMACRO_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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