Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /dts-v1/;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) / {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) 	compatible = "cdns,xtensa-xtfpga";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) 	#address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) 	#size-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 	interrupt-parent = <&pic>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 	chosen {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 		bootargs = "earlycon=cdns,0xfd000000,115200 console=tty0 console=ttyPS0,115200 root=/dev/ram0 rw earlyprintk xilinx_uartps.rx_trigger_level=32 loglevel=8 nohz=off ignore_loglevel";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 	memory@0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 		device_type = "memory";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 		reg = <0x00000000 0x40000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 	cpus {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 		#address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 		#size-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 		cpu@0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 			compatible = "cdns,xtensa-cpu";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 			reg = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 		};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 	pic: pic {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 		compatible = "cdns,xtensa-pic";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 		#interrupt-cells = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 		interrupt-controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 	clocks {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 		osc: main-oscillator {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 			#clock-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 			compatible = "fixed-clock";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 		};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 	soc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 		#address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 		#size-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 		compatible = "simple-bus";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 		ranges = <0x00000000 0xf0000000 0x10000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 		uart0: serial@0d000000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 			compatible = "xlnx,xuartps", "cdns,uart-r1p8";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 			clocks = <&osc>, <&osc>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 			clock-names = "uart_clk", "pclk";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 			reg = <0x0d000000 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 			interrupts = <0 1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 		};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) };