^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) # SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) config XTENSA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) def_bool y
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) select ARCH_32BIT_OFF_T
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) select ARCH_HAS_BINFMT_FLAT if !MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) select ARCH_HAS_DMA_PREP_COHERENT if MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) select ARCH_HAS_SYNC_DMA_FOR_CPU if MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) select ARCH_HAS_SYNC_DMA_FOR_DEVICE if MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) select ARCH_HAS_DMA_SET_UNCACHED if MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) select ARCH_USE_QUEUED_RWLOCKS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) select ARCH_USE_QUEUED_SPINLOCKS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) select ARCH_WANT_FRAME_POINTERS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) select ARCH_WANT_IPC_PARSE_VERSION
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) select BUILDTIME_TABLE_SORT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) select CLONE_BACKWARDS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) select COMMON_CLK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) select DMA_REMAP if MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) select GENERIC_ATOMIC64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) select GENERIC_CLOCKEVENTS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) select GENERIC_IRQ_SHOW
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) select GENERIC_PCI_IOMAP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) select GENERIC_SCHED_CLOCK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) select GENERIC_STRNCPY_FROM_USER if KASAN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) select HAVE_ARCH_AUDITSYSCALL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) select HAVE_ARCH_KASAN if MMU && !XIP_KERNEL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) select HAVE_ARCH_SECCOMP_FILTER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) select HAVE_ARCH_TRACEHOOK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) select HAVE_DEBUG_KMEMLEAK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) select HAVE_DMA_CONTIGUOUS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) select HAVE_EXIT_THREAD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) select HAVE_FUNCTION_TRACER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) select HAVE_FUTEX_CMPXCHG if !MMU && FUTEX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) select HAVE_HW_BREAKPOINT if PERF_EVENTS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) select HAVE_IRQ_TIME_ACCOUNTING
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) select HAVE_OPROFILE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) select HAVE_PCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) select HAVE_PERF_EVENTS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) select HAVE_STACKPROTECTOR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) select HAVE_SYSCALL_TRACEPOINTS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) select IRQ_DOMAIN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) select MODULES_USE_ELF_RELA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) select PERF_USE_VMALLOC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) select SET_FS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) select VIRT_TO_BUS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) Xtensa processors are 32-bit RISC machines designed by Tensilica
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) primarily for embedded systems. These processors are both
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) configurable and extensible. The Linux port to the Xtensa
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) architecture supports all processor configurations and extensions,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) with reasonable minimum requirements. The Xtensa Linux project has
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) a home page at <http://www.linux-xtensa.org/>.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) config GENERIC_HWEIGHT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) def_bool y
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) config ARCH_HAS_ILOG2_U32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) def_bool n
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) config ARCH_HAS_ILOG2_U64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) def_bool n
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) config NO_IOPORT_MAP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) def_bool n
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) config HZ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) default 100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) config LOCKDEP_SUPPORT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) def_bool y
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) config STACKTRACE_SUPPORT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) def_bool y
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) config TRACE_IRQFLAGS_SUPPORT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) def_bool y
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) config MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) def_bool n
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) config HAVE_XTENSA_GPIO32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) def_bool n
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) config KASAN_SHADOW_OFFSET
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) hex
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) default 0x6e400000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) menu "Processor type and features"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) choice
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) prompt "Xtensa Processor Configuration"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) default XTENSA_VARIANT_FSF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) config XTENSA_VARIANT_FSF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) bool "fsf - default (not generic) configuration"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) select MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) config XTENSA_VARIANT_DC232B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) bool "dc232b - Diamond 232L Standard Core Rev.B (LE)"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) select MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) select HAVE_XTENSA_GPIO32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) This variant refers to Tensilica's Diamond 232L Standard core Rev.B (LE).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) config XTENSA_VARIANT_DC233C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) bool "dc233c - Diamond 233L Standard Core Rev.C (LE)"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) select MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) select HAVE_XTENSA_GPIO32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) This variant refers to Tensilica's Diamond 233L Standard core Rev.C (LE).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) config XTENSA_VARIANT_CUSTOM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) bool "Custom Xtensa processor configuration"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) select HAVE_XTENSA_GPIO32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) Select this variant to use a custom Xtensa processor configuration.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) You will be prompted for a processor variant CORENAME.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) endchoice
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) config XTENSA_VARIANT_CUSTOM_NAME
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) string "Xtensa Processor Custom Core Variant Name"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) depends on XTENSA_VARIANT_CUSTOM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) Provide the name of a custom Xtensa processor variant.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) This CORENAME selects arch/xtensa/variant/CORENAME.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) Don't forget you have to select MMU if you have one.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) config XTENSA_VARIANT_NAME
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) string
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) default "dc232b" if XTENSA_VARIANT_DC232B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) default "dc233c" if XTENSA_VARIANT_DC233C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) default "fsf" if XTENSA_VARIANT_FSF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) default XTENSA_VARIANT_CUSTOM_NAME if XTENSA_VARIANT_CUSTOM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) config XTENSA_VARIANT_MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) bool "Core variant has a Full MMU (TLB, Pages, Protection, etc)"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) depends on XTENSA_VARIANT_CUSTOM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) default y
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) select MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) Build a Conventional Kernel with full MMU support,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) ie: it supports a TLB with auto-loading, page protection.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) config XTENSA_VARIANT_HAVE_PERF_EVENTS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) bool "Core variant has Performance Monitor Module"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) depends on XTENSA_VARIANT_CUSTOM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) default n
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) Enable if core variant has Performance Monitor Module with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) External Registers Interface.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) If unsure, say N.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) config XTENSA_FAKE_NMI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) bool "Treat PMM IRQ as NMI"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) depends on XTENSA_VARIANT_HAVE_PERF_EVENTS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) default n
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) If PMM IRQ is the only IRQ at EXCM level it is safe to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) treat it as NMI, which improves accuracy of profiling.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) If there are other interrupts at or above PMM IRQ priority level
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) but not above the EXCM level, PMM IRQ still may be treated as NMI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) but only if these IRQs are not used. There will be a build warning
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) saying that this is not safe, and a bugcheck if one of these IRQs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) actually fire.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) If unsure, say N.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) config XTENSA_UNALIGNED_USER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) bool "Unaligned memory access in user space"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) The Xtensa architecture currently does not handle unaligned
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) memory accesses in hardware but through an exception handler.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) Per default, unaligned memory accesses are disabled in user space.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) Say Y here to enable unaligned memory access in user space.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) config HAVE_SMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) bool "System Supports SMP (MX)"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) depends on XTENSA_VARIANT_CUSTOM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) select XTENSA_MX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) This option is used to indicate that the system-on-a-chip (SOC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) supports Multiprocessing. Multiprocessor support implemented above
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) the CPU core definition and currently needs to be selected manually.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) Multiprocessor support is implemented with external cache and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) interrupt controllers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) The MX interrupt distributer adds Interprocessor Interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) and causes the IRQ numbers to be increased by 4 for devices
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) like the open cores ethernet driver and the serial interface.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) You still have to select "Enable SMP" to enable SMP on this SOC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) config SMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) bool "Enable Symmetric multi-processing support"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) depends on HAVE_SMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) select GENERIC_SMP_IDLE_THREAD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) Enabled SMP Software; allows more than one CPU/CORE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) to be activated during startup.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) config NR_CPUS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) depends on SMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) int "Maximum number of CPUs (2-32)"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) range 2 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) default "4"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) config HOTPLUG_CPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) bool "Enable CPU hotplug support"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) depends on SMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) Say Y here to allow turning CPUs off and on. CPUs can be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) controlled through /sys/devices/system/cpu.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) Say N if you want to disable CPU hotplug.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) config FAST_SYSCALL_XTENSA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) bool "Enable fast atomic syscalls"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) default n
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) fast_syscall_xtensa is a syscall that can make atomic operations
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) on UP kernel when processor has no s32c1i support.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) This syscall is deprecated. It may have issues when called with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) invalid arguments. It is provided only for backwards compatibility.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) Only enable it if your userspace software requires it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) If unsure, say N.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) config FAST_SYSCALL_SPILL_REGISTERS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) bool "Enable spill registers syscall"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) default n
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) fast_syscall_spill_registers is a syscall that spills all active
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) register windows of a calling userspace task onto its stack.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) This syscall is deprecated. It may have issues when called with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) invalid arguments. It is provided only for backwards compatibility.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) Only enable it if your userspace software requires it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) If unsure, say N.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) config USER_ABI_CALL0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) bool
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) choice
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) prompt "Userspace ABI"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) default USER_ABI_DEFAULT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) Select supported userspace ABI.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) If unsure, choose the default ABI.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) config USER_ABI_DEFAULT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) bool "Default ABI only"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) Assume default userspace ABI. For XEA2 cores it is windowed ABI.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) call0 ABI binaries may be run on such kernel, but signal delivery
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) will not work correctly for them.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) config USER_ABI_CALL0_ONLY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) bool "Call0 ABI only"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) select USER_ABI_CALL0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) Select this option to support only call0 ABI in userspace.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) Windowed ABI binaries will crash with a segfault caused by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) an illegal instruction exception on the first 'entry' opcode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) Choose this option if you're planning to run only user code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) built with call0 ABI.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) config USER_ABI_CALL0_PROBE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) bool "Support both windowed and call0 ABI by probing"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) select USER_ABI_CALL0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) Select this option to support both windowed and call0 userspace
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) ABIs. When enabled all processes are started with PS.WOE disabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) and a fast user exception handler for an illegal instruction is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) used to turn on PS.WOE bit on the first 'entry' opcode executed by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) the userspace.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) This option should be enabled for the kernel that must support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) both call0 and windowed ABIs in userspace at the same time.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) Note that Xtensa ISA does not guarantee that entry opcode will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) raise an illegal instruction exception on cores with XEA2 when
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) PS.WOE is disabled, check whether the target core supports it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) endchoice
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) endmenu
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) config XTENSA_CALIBRATE_CCOUNT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) def_bool n
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) On some platforms (XT2000, for example), the CPU clock rate can
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) vary. The frequency can be determined, however, by measuring
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) against a well known, fixed frequency, such as an UART oscillator.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) config SERIAL_CONSOLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) def_bool n
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) config PLATFORM_HAVE_XIP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) def_bool n
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) menu "Platform options"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) choice
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) prompt "Xtensa System Type"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) default XTENSA_PLATFORM_ISS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) config XTENSA_PLATFORM_ISS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) bool "ISS"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) select XTENSA_CALIBRATE_CCOUNT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) select SERIAL_CONSOLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) ISS is an acronym for Tensilica's Instruction Set Simulator.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) config XTENSA_PLATFORM_XT2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) bool "XT2000"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) select HAVE_IDE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) XT2000 is the name of Tensilica's feature-rich emulation platform.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) This hardware is capable of running a full Linux distribution.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) config XTENSA_PLATFORM_XTFPGA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) bool "XTFPGA"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) select ETHOC if ETHERNET
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) select PLATFORM_WANT_DEFAULT_MEM if !MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) select SERIAL_CONSOLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) select XTENSA_CALIBRATE_CCOUNT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) select PLATFORM_HAVE_XIP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) XTFPGA is the name of Tensilica board family (LX60, LX110, LX200, ML605).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) This hardware is capable of running a full Linux distribution.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) endchoice
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) config PLATFORM_NR_IRQS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) default 3 if XTENSA_PLATFORM_XT2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) default 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) config XTENSA_CPU_CLOCK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) int "CPU clock rate [MHz]"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) depends on !XTENSA_CALIBRATE_CCOUNT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) default 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) config GENERIC_CALIBRATE_DELAY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) bool "Auto calibration of the BogoMIPS value"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) The BogoMIPS value can easily be derived from the CPU frequency.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) config CMDLINE_BOOL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) bool "Default bootloader kernel arguments"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) config CMDLINE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) string "Initial kernel command string"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) depends on CMDLINE_BOOL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) default "console=ttyS0,38400 root=/dev/ram"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) On some architectures (EBSA110 and CATS), there is currently no way
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) for the boot loader to pass arguments to the kernel. For these
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) architectures, you should supply some command-line options at build
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) time by entering them here. As a minimum, you should specify the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) memory size and the root device (e.g., mem=64M root=/dev/nfs).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) config USE_OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) bool "Flattened Device Tree support"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) select OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) select OF_EARLY_FLATTREE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) Include support for flattened device tree machine descriptions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) config BUILTIN_DTB_SOURCE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) string "DTB to build into the kernel image"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) depends on OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) config PARSE_BOOTPARAM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) bool "Parse bootparam block"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) default y
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) Parse parameters passed to the kernel from the bootloader. It may
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) be disabled if the kernel is known to run without the bootloader.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) If unsure, say Y.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) config BLK_DEV_SIMDISK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) tristate "Host file-based simulated block device support"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) default n
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) depends on XTENSA_PLATFORM_ISS && BLOCK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) Create block devices that map to files in the host file system.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) Device binding to host file may be changed at runtime via proc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) interface provided the device is not in use.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) config BLK_DEV_SIMDISK_COUNT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) int "Number of host file-based simulated block devices"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) range 1 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) depends on BLK_DEV_SIMDISK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) default 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) This is the default minimal number of created block devices.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) Kernel/module parameter 'simdisk_count' may be used to change this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) value at runtime. More file names (but no more than 10) may be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) specified as parameters, simdisk_count grows accordingly.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) config SIMDISK0_FILENAME
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) string "Host filename for the first simulated device"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) depends on BLK_DEV_SIMDISK = y
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) default ""
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) Attach a first simdisk to a host file. Conventionally, this file
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) contains a root file system.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) config SIMDISK1_FILENAME
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) string "Host filename for the second simulated device"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) depends on BLK_DEV_SIMDISK = y && BLK_DEV_SIMDISK_COUNT != 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) default ""
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) Another simulated disk in a host file for a buildroot-independent
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) storage.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) config XTFPGA_LCD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) bool "Enable XTFPGA LCD driver"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) depends on XTENSA_PLATFORM_XTFPGA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) default n
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) There's a 2x16 LCD on most of XTFPGA boards, kernel may output
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) progress messages there during bootup/shutdown. It may be useful
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) during board bringup.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) If unsure, say N.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) config XTFPGA_LCD_BASE_ADDR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) hex "XTFPGA LCD base address"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) depends on XTFPGA_LCD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) default "0x0d0c0000"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) Base address of the LCD controller inside KIO region.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) Different boards from XTFPGA family have LCD controller at different
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) addresses. Please consult prototyping user guide for your board for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) the correct address. Wrong address here may lead to hardware lockup.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) config XTFPGA_LCD_8BIT_ACCESS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) bool "Use 8-bit access to XTFPGA LCD"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) depends on XTFPGA_LCD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) default n
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) LCD may be connected with 4- or 8-bit interface, 8-bit access may
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) only be used with 8-bit interface. Please consult prototyping user
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) guide for your board for the correct interface width.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) comment "Kernel memory layout"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) config INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) bool "Initialize Xtensa MMU inside the Linux kernel code"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) depends on !XTENSA_VARIANT_FSF && !XTENSA_VARIANT_DC232B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) default y if XTENSA_VARIANT_DC233C || XTENSA_VARIANT_CUSTOM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) Earlier version initialized the MMU in the exception vector
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) before jumping to _startup in head.S and had an advantage that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) it was possible to place a software breakpoint at 'reset' and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) then enter your normal kernel breakpoints once the MMU was mapped
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) to the kernel mappings (0XC0000000).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) This unfortunately won't work for U-Boot and likely also wont
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) work for using KEXEC to have a hot kernel ready for doing a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) KDUMP.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) So now the MMU is initialized in head.S but it's necessary to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) use hardware breakpoints (gdb 'hbreak' cmd) to break at _startup.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) xt-gdb can't place a Software Breakpoint in the 0XD region prior
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) to mapping the MMU and after mapping even if the area of low memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) was mapped gdb wouldn't remove the breakpoint on hitting it as the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) PC wouldn't match. Since Hardware Breakpoints are recommended for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) Linux configurations it seems reasonable to just assume they exist
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) and leave this older mechanism for unfortunate souls that choose
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) not to follow Tensilica's recommendation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) Selecting this will cause U-Boot to set the KERNEL Load and Entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) address at 0x00003000 instead of the mapped std of 0xD0003000.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) If in doubt, say Y.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) config XIP_KERNEL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) bool "Kernel Execute-In-Place from ROM"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) depends on PLATFORM_HAVE_XIP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) Execute-In-Place allows the kernel to run from non-volatile storage
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) directly addressable by the CPU, such as NOR flash. This saves RAM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) space since the text section of the kernel is not loaded from flash
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) to RAM. Read-write sections, such as the data section and stack,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) are still copied to RAM. The XIP kernel is not compressed since
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) it has to run directly from flash, so it will take more space to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) store it. The flash address used to link the kernel object files,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) and for storing it, is configuration dependent. Therefore, if you
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) say Y here, you must know the proper physical address where to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) store the kernel image depending on your own flash memory usage.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) Also note that the make target becomes "make xipImage" rather than
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) "make Image" or "make uImage". The final kernel binary to put in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) ROM memory will be arch/xtensa/boot/xipImage.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) If unsure, say N.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) config MEMMAP_CACHEATTR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) hex "Cache attributes for the memory address space"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) depends on !MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) default 0x22222222
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) These cache attributes are set up for noMMU systems. Each hex digit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) specifies cache attributes for the corresponding 512MB memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) region: bits 0..3 -- for addresses 0x00000000..0x1fffffff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) bits 4..7 -- for addresses 0x20000000..0x3fffffff, and so on.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) Cache attribute values are specific for the MMU type.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) For region protection MMUs:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) 1: WT cached,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) 2: cache bypass,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) 4: WB cached,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) f: illegal.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) For full MMU:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) bit 0: executable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) bit 1: writable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) bits 2..3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) 0: cache bypass,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) 1: WB cache,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) 2: WT cache,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) 3: special (c and e are illegal, f is reserved).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) For MPU:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) 0: illegal,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) 1: WB cache,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) 2: WB, no-write-allocate cache,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) 3: WT cache,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) 4: cache bypass.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) config KSEG_PADDR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) hex "Physical address of the KSEG mapping"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) depends on INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX && MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) default 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) This is the physical address where KSEG is mapped. Please refer to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) the chosen KSEG layout help for the required address alignment.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) Unpacked kernel image (including vectors) must be located completely
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) within KSEG.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) Physical memory below this address is not available to linux.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) If unsure, leave the default value here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) config KERNEL_VIRTUAL_ADDRESS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) hex "Kernel virtual address"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) depends on MMU && XIP_KERNEL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) default 0xd0003000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) This is the virtual address where the XIP kernel is mapped.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) XIP kernel may be mapped into KSEG or KIO region, virtual address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) provided here must match kernel load address provided in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) KERNEL_LOAD_ADDRESS.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) config KERNEL_LOAD_ADDRESS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) hex "Kernel load address"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) default 0x60003000 if !MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) default 0x00003000 if MMU && INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) default 0xd0003000 if MMU && !INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) This is the address where the kernel is loaded.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) It is virtual address for MMUv2 configurations and physical address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) for all other configurations.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) If unsure, leave the default value here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) choice
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) prompt "Relocatable vectors location"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) default XTENSA_VECTORS_IN_TEXT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) Choose whether relocatable vectors are merged into the kernel .text
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) or placed separately at runtime. This option does not affect
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) configurations without VECBASE register where vectors are always
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) placed at their hardware-defined locations.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) config XTENSA_VECTORS_IN_TEXT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) bool "Merge relocatable vectors into kernel text"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) depends on !MTD_XIP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) This option puts relocatable vectors into the kernel .text section
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) with proper alignment.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) This is a safe choice for most configurations.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) config XTENSA_VECTORS_SEPARATE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) bool "Put relocatable vectors at fixed address"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) This option puts relocatable vectors at specific virtual address.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) Vectors are merged with the .init data in the kernel image and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) are copied into their designated location during kernel startup.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) Use it to put vectors into IRAM or out of FLASH on kernels with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) XIP-aware MTD support.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) endchoice
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) config VECTORS_ADDR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) hex "Kernel vectors virtual address"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) default 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) depends on XTENSA_VECTORS_SEPARATE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) This is the virtual address of the (relocatable) vectors base.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) It must be within KSEG if MMU is used.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) config XIP_DATA_ADDR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) hex "XIP kernel data virtual address"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) depends on XIP_KERNEL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) default 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) This is the virtual address where XIP kernel data is copied.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) It must be within KSEG if MMU is used.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) config PLATFORM_WANT_DEFAULT_MEM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) def_bool n
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) config DEFAULT_MEM_START
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) hex
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) prompt "PAGE_OFFSET/PHYS_OFFSET" if !MMU && PLATFORM_WANT_DEFAULT_MEM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) default 0x60000000 if PLATFORM_WANT_DEFAULT_MEM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) default 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) This is the base address used for both PAGE_OFFSET and PHYS_OFFSET
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) in noMMU configurations.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) If unsure, leave the default value here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) choice
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) prompt "KSEG layout"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) depends on MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) default XTENSA_KSEG_MMU_V2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) config XTENSA_KSEG_MMU_V2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) bool "MMUv2: 128MB cached + 128MB uncached"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) MMUv2 compatible kernel memory map: TLB way 5 maps 128MB starting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) at KSEG_PADDR to 0xd0000000 with cache and to 0xd8000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) without cache.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) KSEG_PADDR must be aligned to 128MB.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) config XTENSA_KSEG_256M
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) bool "256MB cached + 256MB uncached"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) depends on INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) TLB way 6 maps 256MB starting at KSEG_PADDR to 0xb0000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) with cache and to 0xc0000000 without cache.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) KSEG_PADDR must be aligned to 256MB.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) config XTENSA_KSEG_512M
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) bool "512MB cached + 512MB uncached"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) depends on INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) TLB way 6 maps 512MB starting at KSEG_PADDR to 0xa0000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) with cache and to 0xc0000000 without cache.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) KSEG_PADDR must be aligned to 256MB.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) endchoice
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) config HIGHMEM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) bool "High Memory Support"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) depends on MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) Linux can use the full amount of RAM in the system by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) default. However, the default MMUv2 setup only maps the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) lowermost 128 MB of memory linearly to the areas starting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) at 0xd0000000 (cached) and 0xd8000000 (uncached).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) When there are more than 128 MB memory in the system not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) all of it can be "permanently mapped" by the kernel.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) The physical memory that's not permanently mapped is called
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) "high memory".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) If you are compiling a kernel which will never run on a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) machine with more than 128 MB total physical RAM, answer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) N here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) If unsure, say Y.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) config FORCE_MAX_ZONEORDER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) int "Maximum zone order"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) default "11"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) The kernel memory allocator divides physically contiguous memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) blocks into "zones", where each zone is a power of two number of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) pages. This option selects the largest power of two that the kernel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) keeps in the memory allocator. If you need to allocate very large
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) blocks of physically contiguous memory, then you may need to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) increase this value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) This config option is actually maximum order plus one. For example,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) a value of 11 means that the largest free memory block is 2^10 pages.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) endmenu
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) menu "Power management options"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) source "kernel/power/Kconfig"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) endmenu
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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