^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Xen PCI - handle PCI (INTx) and MSI infrastructure calls for PV, HVM and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * initial domain support. We also handle the DSDT _PRT callbacks for GSI's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * used in HVM and initial domain mode (PV does not parse ACPI, so it has no
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * concept of GSIs). Under PV we hook under the pnbbios API for IRQs and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * 0xcf8 PCI configuration read/write.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Author: Ryan Wilson <hap9@epoch.ncsc.mil>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Stefano Stabellini <stefano.stabellini@eu.citrix.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/export.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/acpi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <asm/io_apic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <asm/pci_x86.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <asm/xen/hypervisor.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <xen/features.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <xen/events.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <asm/xen/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <asm/xen/cpuid.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <asm/apic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <asm/acpi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <asm/i8259.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) static int xen_pcifront_enable_irq(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) int share = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) int pirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) u8 gsi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) rc = pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &gsi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) if (rc < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) dev_warn(&dev->dev, "Xen PCI: failed to read interrupt line: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) /* In PV DomU the Xen PCI backend puts the PIRQ in the interrupt line.*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) pirq = gsi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) if (gsi < nr_legacy_irqs())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) share = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) rc = xen_bind_pirq_gsi_to_irq(gsi, pirq, share, "pcifront");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) if (rc < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) dev_warn(&dev->dev, "Xen PCI: failed to bind GSI%d (PIRQ%d) to IRQ: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) gsi, pirq, rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) dev->irq = rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) dev_info(&dev->dev, "Xen PCI mapped GSI%d to IRQ%d\n", gsi, dev->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #ifdef CONFIG_ACPI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) static int xen_register_pirq(u32 gsi, int triggering, bool set_pirq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) int rc, pirq = -1, irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) struct physdev_map_pirq map_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) int shareable = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) irq = xen_irq_from_gsi(gsi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) if (irq > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) return irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) if (set_pirq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) pirq = gsi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) map_irq.domid = DOMID_SELF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) map_irq.type = MAP_PIRQ_TYPE_GSI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) map_irq.index = gsi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) map_irq.pirq = pirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) rc = HYPERVISOR_physdev_op(PHYSDEVOP_map_pirq, &map_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) printk(KERN_WARNING "xen map irq failed %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) if (triggering == ACPI_EDGE_SENSITIVE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) shareable = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) name = "ioapic-edge";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) shareable = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) name = "ioapic-level";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) irq = xen_bind_pirq_gsi_to_irq(gsi, map_irq.pirq, shareable, name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) if (irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) printk(KERN_DEBUG "xen: --> pirq=%d -> irq=%d (gsi=%d)\n", map_irq.pirq, irq, gsi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) return irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) static int acpi_register_gsi_xen_hvm(struct device *dev, u32 gsi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) int trigger, int polarity)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) if (!xen_hvm_domain())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) return xen_register_pirq(gsi, trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) false /* no mapping of GSI to PIRQ */);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #ifdef CONFIG_XEN_DOM0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) static int xen_register_gsi(u32 gsi, int triggering, int polarity)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) int rc, irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) struct physdev_setup_gsi setup_gsi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) if (!xen_pv_domain())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) printk(KERN_DEBUG "xen: registering gsi %u triggering %d polarity %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) gsi, triggering, polarity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) irq = xen_register_pirq(gsi, triggering, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) setup_gsi.gsi = gsi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) setup_gsi.triggering = (triggering == ACPI_EDGE_SENSITIVE ? 0 : 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) setup_gsi.polarity = (polarity == ACPI_ACTIVE_HIGH ? 0 : 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) rc = HYPERVISOR_physdev_op(PHYSDEVOP_setup_gsi, &setup_gsi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) if (rc == -EEXIST)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) printk(KERN_INFO "Already setup the GSI :%d\n", gsi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) else if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) printk(KERN_ERR "Failed to setup GSI :%d, err_code:%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) gsi, rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) return irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) static int acpi_register_gsi_xen(struct device *dev, u32 gsi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) int trigger, int polarity)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) return xen_register_gsi(gsi, trigger, polarity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #if defined(CONFIG_PCI_MSI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #include <linux/msi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #include <asm/msidef.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) struct xen_pci_frontend_ops *xen_pci_frontend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) EXPORT_SYMBOL_GPL(xen_pci_frontend);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) struct xen_msi_ops {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) int (*setup_msi_irqs)(struct pci_dev *dev, int nvec, int type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) void (*teardown_msi_irqs)(struct pci_dev *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) static struct xen_msi_ops xen_msi_ops __ro_after_init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) static int xen_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) int irq, ret, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) struct msi_desc *msidesc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) int *v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) if (type == PCI_CAP_ID_MSI && nvec > 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) v = kcalloc(max(1, nvec), sizeof(int), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) if (!v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) if (type == PCI_CAP_ID_MSIX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) ret = xen_pci_frontend_enable_msix(dev, v, nvec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) ret = xen_pci_frontend_enable_msi(dev, v);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) for_each_pci_msi_entry(msidesc, dev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) irq = xen_bind_pirq_msi_to_irq(dev, msidesc, v[i],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) (type == PCI_CAP_ID_MSI) ? nvec : 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) (type == PCI_CAP_ID_MSIX) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) "pcifront-msi-x" :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) "pcifront-msi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) DOMID_SELF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) if (irq < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) ret = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) goto free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) i++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) kfree(v);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) if (ret == -ENOSYS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) dev_err(&dev->dev, "Xen PCI frontend has not registered MSI/MSI-X support!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) else if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) dev_err(&dev->dev, "Xen PCI frontend error: %d!\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) free:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) kfree(v);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define XEN_PIRQ_MSI_DATA (MSI_DATA_TRIGGER_EDGE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) MSI_DATA_LEVEL_ASSERT | (3 << 8) | MSI_DATA_VECTOR(0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) static void xen_msi_compose_msg(struct pci_dev *pdev, unsigned int pirq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) struct msi_msg *msg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) /* We set vector == 0 to tell the hypervisor we don't care about it,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) * but we want a pirq setup instead.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) * We use the dest_id field to pass the pirq that we want. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) msg->address_hi = MSI_ADDR_BASE_HI | MSI_ADDR_EXT_DEST_ID(pirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) msg->address_lo =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) MSI_ADDR_BASE_LO |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) MSI_ADDR_DEST_MODE_PHYSICAL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) MSI_ADDR_REDIRECTION_CPU |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) MSI_ADDR_DEST_ID(pirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) msg->data = XEN_PIRQ_MSI_DATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) static int xen_hvm_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) int irq, pirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) struct msi_desc *msidesc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) struct msi_msg msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) if (type == PCI_CAP_ID_MSI && nvec > 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) for_each_pci_msi_entry(msidesc, dev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) pirq = xen_allocate_pirq_msi(dev, msidesc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) if (pirq < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) irq = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) xen_msi_compose_msg(dev, pirq, &msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) __pci_write_msi_msg(msidesc, &msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) dev_dbg(&dev->dev, "xen: msi bound to pirq=%d\n", pirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) irq = xen_bind_pirq_msi_to_irq(dev, msidesc, pirq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) (type == PCI_CAP_ID_MSI) ? nvec : 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) (type == PCI_CAP_ID_MSIX) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) "msi-x" : "msi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) DOMID_SELF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) if (irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) dev_dbg(&dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) "xen: msi --> pirq=%d --> irq=%d\n", pirq, irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) dev_err(&dev->dev, "Failed to create MSI%s! ret=%d!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) type == PCI_CAP_ID_MSI ? "" : "-X", irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) return irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #ifdef CONFIG_XEN_DOM0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) static bool __read_mostly pci_seg_supported = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) static int xen_initdom_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) struct msi_desc *msidesc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) for_each_pci_msi_entry(msidesc, dev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) struct physdev_map_pirq map_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) domid_t domid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) domid = ret = xen_find_device_domain_owner(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) /* N.B. Casting int's -ENODEV to uint16_t results in 0xFFED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) * hence check ret value for < 0. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) domid = DOMID_SELF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) memset(&map_irq, 0, sizeof(map_irq));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) map_irq.domid = domid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) map_irq.type = MAP_PIRQ_TYPE_MSI_SEG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) map_irq.index = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) map_irq.pirq = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) map_irq.bus = dev->bus->number |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) (pci_domain_nr(dev->bus) << 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) map_irq.devfn = dev->devfn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) if (type == PCI_CAP_ID_MSI && nvec > 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) map_irq.type = MAP_PIRQ_TYPE_MULTI_MSI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) map_irq.entry_nr = nvec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) } else if (type == PCI_CAP_ID_MSIX) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) int pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) u32 table_offset, bir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) pos = dev->msix_cap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) pci_read_config_dword(dev, pos + PCI_MSIX_TABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) &table_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) bir = (u8)(table_offset & PCI_MSIX_TABLE_BIR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) flags = pci_resource_flags(dev, bir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) if (!flags || (flags & IORESOURCE_UNSET))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) map_irq.table_base = pci_resource_start(dev, bir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) map_irq.entry_nr = msidesc->msi_attrib.entry_nr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) if (pci_seg_supported)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) ret = HYPERVISOR_physdev_op(PHYSDEVOP_map_pirq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) &map_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) if (type == PCI_CAP_ID_MSI && nvec > 1 && ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) * If MAP_PIRQ_TYPE_MULTI_MSI is not available
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) * there's nothing else we can do in this case.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) * Just set ret > 0 so driver can retry with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) * single MSI.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) ret = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) if (ret == -EINVAL && !pci_domain_nr(dev->bus)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) map_irq.type = MAP_PIRQ_TYPE_MSI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) map_irq.index = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) map_irq.pirq = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) map_irq.bus = dev->bus->number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) ret = HYPERVISOR_physdev_op(PHYSDEVOP_map_pirq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) &map_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) if (ret != -EINVAL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) pci_seg_supported = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) dev_warn(&dev->dev, "xen map irq failed %d for %d domain\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) ret, domid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) ret = xen_bind_pirq_msi_to_irq(dev, msidesc, map_irq.pirq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) (type == PCI_CAP_ID_MSI) ? nvec : 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) (type == PCI_CAP_ID_MSIX) ? "msi-x" : "msi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) domid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) static void xen_initdom_restore_msi_irqs(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) if (pci_seg_supported) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) struct physdev_pci_device restore_ext;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) restore_ext.seg = pci_domain_nr(dev->bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) restore_ext.bus = dev->bus->number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) restore_ext.devfn = dev->devfn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) ret = HYPERVISOR_physdev_op(PHYSDEVOP_restore_msi_ext,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) &restore_ext);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) if (ret == -ENOSYS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) pci_seg_supported = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) WARN(ret && ret != -ENOSYS, "restore_msi_ext -> %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) if (!pci_seg_supported) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) struct physdev_restore_msi restore;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) restore.bus = dev->bus->number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) restore.devfn = dev->devfn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) ret = HYPERVISOR_physdev_op(PHYSDEVOP_restore_msi, &restore);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) WARN(ret && ret != -ENOSYS, "restore_msi -> %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) #else /* CONFIG_XEN_DOM0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) #define xen_initdom_setup_msi_irqs NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) #define xen_initdom_restore_msi_irqs NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) #endif /* !CONFIG_XEN_DOM0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) static void xen_teardown_msi_irqs(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) struct msi_desc *msidesc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) for_each_pci_msi_entry(msidesc, dev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) if (msidesc->irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) for (i = 0; i < msidesc->nvec_used; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) xen_destroy_irq(msidesc->irq + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) static void xen_pv_teardown_msi_irqs(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) struct msi_desc *msidesc = first_pci_msi_entry(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) if (msidesc->msi_attrib.is_msix)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) xen_pci_frontend_disable_msix(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) xen_pci_frontend_disable_msi(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) xen_teardown_msi_irqs(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) static int xen_msi_domain_alloc_irqs(struct irq_domain *domain,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) struct device *dev, int nvec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) int type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) if (WARN_ON_ONCE(!dev_is_pci(dev)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) if (first_msi_entry(dev)->msi_attrib.is_msix)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) type = PCI_CAP_ID_MSIX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) type = PCI_CAP_ID_MSI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) return xen_msi_ops.setup_msi_irqs(to_pci_dev(dev), nvec, type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) static void xen_msi_domain_free_irqs(struct irq_domain *domain,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) if (WARN_ON_ONCE(!dev_is_pci(dev)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) xen_msi_ops.teardown_msi_irqs(to_pci_dev(dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) static struct msi_domain_ops xen_pci_msi_domain_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) .domain_alloc_irqs = xen_msi_domain_alloc_irqs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) .domain_free_irqs = xen_msi_domain_free_irqs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) static struct msi_domain_info xen_pci_msi_domain_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) .ops = &xen_pci_msi_domain_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) * This irq domain is a blatant violation of the irq domain design, but
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) * distangling XEN into real irq domains is not a job for mere mortals with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) * limited XENology. But it's the least dangerous way for a mere mortal to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) * get rid of the arch_*_msi_irqs() hackery in order to store the irq
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) * domain pointer in struct device. This irq domain wrappery allows to do
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) * that without breaking XEN terminally.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) static __init struct irq_domain *xen_create_pci_msi_domain(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) struct irq_domain *d = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) struct fwnode_handle *fn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) fn = irq_domain_alloc_named_fwnode("XEN-MSI");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) if (fn)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) d = msi_create_irq_domain(fn, &xen_pci_msi_domain_info, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) /* FIXME: No idea how to survive if this fails */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) BUG_ON(!d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) return d;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) static __init void xen_setup_pci_msi(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) if (xen_pv_domain()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) if (xen_initial_domain()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) xen_msi_ops.setup_msi_irqs = xen_initdom_setup_msi_irqs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) x86_msi.restore_msi_irqs = xen_initdom_restore_msi_irqs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) xen_msi_ops.setup_msi_irqs = xen_setup_msi_irqs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) xen_msi_ops.teardown_msi_irqs = xen_pv_teardown_msi_irqs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) pci_msi_ignore_mask = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) } else if (xen_hvm_domain()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) xen_msi_ops.setup_msi_irqs = xen_hvm_setup_msi_irqs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) xen_msi_ops.teardown_msi_irqs = xen_teardown_msi_irqs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) WARN_ON_ONCE(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) * Override the PCI/MSI irq domain init function. No point
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) * in allocating the native domain and never use it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) x86_init.irqs.create_pci_msi_domain = xen_create_pci_msi_domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) #else /* CONFIG_PCI_MSI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) static inline void xen_setup_pci_msi(void) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) #endif /* CONFIG_PCI_MSI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) int __init pci_xen_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) if (!xen_pv_domain() || xen_initial_domain())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) printk(KERN_INFO "PCI: setting up Xen PCI frontend stub\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) pcibios_set_cache_line_size();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) pcibios_enable_irq = xen_pcifront_enable_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) pcibios_disable_irq = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) /* Keep ACPI out of the picture */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) acpi_noirq_set();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) xen_setup_pci_msi();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) #ifdef CONFIG_PCI_MSI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) static void __init xen_hvm_msi_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) if (!disable_apic) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) * If hardware supports (x2)APIC virtualization (as indicated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) * by hypervisor's leaf 4) then we don't need to use pirqs/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) * event channels for MSI handling and instead use regular
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) * APIC processing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) uint32_t eax = cpuid_eax(xen_cpuid_base() + 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) if (((eax & XEN_HVM_CPUID_X2APIC_VIRT) && x2apic_mode) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) ((eax & XEN_HVM_CPUID_APIC_ACCESS_VIRT) && boot_cpu_has(X86_FEATURE_APIC)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) xen_setup_pci_msi();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) int __init pci_xen_hvm_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) if (!xen_have_vector_callback || !xen_feature(XENFEAT_hvm_pirqs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) #ifdef CONFIG_ACPI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) * We don't want to change the actual ACPI delivery model,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) * just how GSIs get registered.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) __acpi_register_gsi = acpi_register_gsi_xen_hvm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) __acpi_unregister_gsi = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) #ifdef CONFIG_PCI_MSI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) * We need to wait until after x2apic is initialized
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) * before we can set MSI IRQ ops.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) x86_platform.apic_post_init = xen_hvm_msi_init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) #ifdef CONFIG_XEN_DOM0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) int __init pci_xen_initial_domain(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) xen_setup_pci_msi();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) __acpi_register_gsi = acpi_register_gsi_xen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) __acpi_unregister_gsi = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) * Pre-allocate the legacy IRQs. Use NR_LEGACY_IRQS here
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) * because we don't have a PIC and thus nr_legacy_irqs() is zero.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) for (irq = 0; irq < NR_IRQS_LEGACY; irq++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) int trigger, polarity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) if (acpi_get_override_irq(irq, &trigger, &polarity) == -1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) xen_register_pirq(irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) trigger ? ACPI_LEVEL_SENSITIVE : ACPI_EDGE_SENSITIVE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) true /* Map GSI to PIRQ */);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) if (0 == nr_ioapics) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) for (irq = 0; irq < nr_legacy_irqs(); irq++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) xen_bind_pirq_gsi_to_irq(irq, irq, 0, "xt-pic");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) struct xen_device_domain_owner {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) domid_t domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) struct pci_dev *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) struct list_head list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) static DEFINE_SPINLOCK(dev_domain_list_spinlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) static struct list_head dev_domain_list = LIST_HEAD_INIT(dev_domain_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) static struct xen_device_domain_owner *find_device(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) struct xen_device_domain_owner *owner;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) list_for_each_entry(owner, &dev_domain_list, list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) if (owner->dev == dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) return owner;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) int xen_find_device_domain_owner(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) struct xen_device_domain_owner *owner;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) int domain = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) spin_lock(&dev_domain_list_spinlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) owner = find_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) if (owner)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) domain = owner->domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) spin_unlock(&dev_domain_list_spinlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) return domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) EXPORT_SYMBOL_GPL(xen_find_device_domain_owner);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) int xen_register_device_domain_owner(struct pci_dev *dev, uint16_t domain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) struct xen_device_domain_owner *owner;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) owner = kzalloc(sizeof(struct xen_device_domain_owner), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) if (!owner)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) spin_lock(&dev_domain_list_spinlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) if (find_device(dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) spin_unlock(&dev_domain_list_spinlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) kfree(owner);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) return -EEXIST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) owner->domain = domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) owner->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) list_add_tail(&owner->list, &dev_domain_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) spin_unlock(&dev_domain_list_spinlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) EXPORT_SYMBOL_GPL(xen_register_device_domain_owner);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) int xen_unregister_device_domain_owner(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) struct xen_device_domain_owner *owner;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) spin_lock(&dev_domain_list_spinlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) owner = find_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) if (!owner) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) spin_unlock(&dev_domain_list_spinlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) list_del(&owner->list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) spin_unlock(&dev_domain_list_spinlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) kfree(owner);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) EXPORT_SYMBOL_GPL(xen_unregister_device_domain_owner);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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