^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * DMA translation between STA2x11 AMBA memory mapping and the x86 memory mapping
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * ST Microelectronics ConneXt (STA2X11/STA2X10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (c) 2010-2011 Wind River Systems, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/pci_ids.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/export.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/list.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/dma-direct.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <asm/iommu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define STA2X11_SWIOTLB_SIZE (4*1024*1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * We build a list of bus numbers that are under the ConneXt. The
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * main bridge hosts 4 busses, which are the 4 endpoints, in order.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define STA2X11_NR_EP 4 /* 0..3 included */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define STA2X11_NR_FUNCS 8 /* 0..7 included */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define STA2X11_AMBA_SIZE (512 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) struct sta2x11_ahb_regs { /* saved during suspend */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) u32 base, pexlbase, pexhbase, crw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) struct sta2x11_mapping {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) int is_suspended;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) struct sta2x11_ahb_regs regs[STA2X11_NR_FUNCS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) struct sta2x11_instance {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) struct list_head list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) int bus0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) struct sta2x11_mapping map[STA2X11_NR_EP];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) static LIST_HEAD(sta2x11_instance_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) /* At probe time, record new instances of this bridge (likely one only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) static void sta2x11_new_instance(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) struct sta2x11_instance *instance;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) instance = kzalloc(sizeof(*instance), GFP_ATOMIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) if (!instance)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) /* This has a subordinate bridge, with 4 more-subordinate ones */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) instance->bus0 = pdev->subordinate->number + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) if (list_empty(&sta2x11_instance_list)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) int size = STA2X11_SWIOTLB_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) /* First instance: register your own swiotlb area */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) dev_info(&pdev->dev, "Using SWIOTLB (size %i)\n", size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) if (swiotlb_late_init_with_default_size(size))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) dev_emerg(&pdev->dev, "init swiotlb failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) list_add(&instance->list, &sta2x11_instance_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_STMICRO, 0xcc17, sta2x11_new_instance);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * Utility functions used in this file from below
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) static struct sta2x11_instance *sta2x11_pdev_to_instance(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) struct sta2x11_instance *instance;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) int ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) list_for_each_entry(instance, &sta2x11_instance_list, list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) ep = pdev->bus->number - instance->bus0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) if (ep >= 0 && ep < STA2X11_NR_EP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) return instance;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) static int sta2x11_pdev_to_ep(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) struct sta2x11_instance *instance;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) instance = sta2x11_pdev_to_instance(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) if (!instance)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) return pdev->bus->number - instance->bus0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) /* This is exported, as some devices need to access the MFD registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) struct sta2x11_instance *sta2x11_get_instance(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) return sta2x11_pdev_to_instance(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) EXPORT_SYMBOL(sta2x11_get_instance);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) /* At setup time, we use our own ops if the device is a ConneXt one */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) static void sta2x11_setup_pdev(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) struct sta2x11_instance *instance = sta2x11_pdev_to_instance(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) if (!instance) /* either a sta2x11 bridge or another ST device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) /* We must enable all devices as master, for audio DMA to work */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) pci_set_master(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_STMICRO, PCI_ANY_ID, sta2x11_setup_pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) * At boot we must set up the mappings for the pcie-to-amba bridge.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) * It involves device access, and the same happens at suspend/resume time
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define AHB_MAPB 0xCA4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define AHB_CRW(i) (AHB_MAPB + 0 + (i) * 0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define AHB_CRW_SZMASK 0xfffffc00UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define AHB_CRW_ENABLE (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define AHB_CRW_WTYPE_MEM (2 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define AHB_CRW_ROE (1UL << 3) /* Relax Order Ena */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define AHB_CRW_NSE (1UL << 4) /* No Snoop Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define AHB_BASE(i) (AHB_MAPB + 4 + (i) * 0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define AHB_PEXLBASE(i) (AHB_MAPB + 8 + (i) * 0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define AHB_PEXHBASE(i) (AHB_MAPB + 12 + (i) * 0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) /* At probe time, enable mapping for each endpoint, using the pdev */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) static void sta2x11_map_ep(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) struct sta2x11_instance *instance = sta2x11_pdev_to_instance(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) u32 amba_base, max_amba_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) if (!instance)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) pci_read_config_dword(pdev, AHB_BASE(0), &amba_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) max_amba_addr = amba_base + STA2X11_AMBA_SIZE - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) ret = dma_direct_set_offset(dev, 0, amba_base, STA2X11_AMBA_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) dev_err(dev, "sta2x11: could not set DMA offset\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) dev->bus_dma_limit = max_amba_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) pci_set_consistent_dma_mask(pdev, max_amba_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) pci_set_dma_mask(pdev, max_amba_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) /* Configure AHB mapping */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) pci_write_config_dword(pdev, AHB_PEXLBASE(0), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) pci_write_config_dword(pdev, AHB_PEXHBASE(0), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) pci_write_config_dword(pdev, AHB_CRW(0), STA2X11_AMBA_SIZE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) AHB_CRW_WTYPE_MEM | AHB_CRW_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) /* Disable all the other windows */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) for (i = 1; i < STA2X11_NR_FUNCS; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) pci_write_config_dword(pdev, AHB_CRW(i), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) dev_info(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) "sta2x11: Map EP %i: AMBA address %#8x-%#8x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) sta2x11_pdev_to_ep(pdev), amba_base, max_amba_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_STMICRO, PCI_ANY_ID, sta2x11_map_ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #ifdef CONFIG_PM /* Some register values must be saved and restored */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) static struct sta2x11_mapping *sta2x11_pdev_to_mapping(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) struct sta2x11_instance *instance;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) int ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) instance = sta2x11_pdev_to_instance(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) if (!instance)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) ep = sta2x11_pdev_to_ep(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) return instance->map + ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) static void suspend_mapping(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) struct sta2x11_mapping *map = sta2x11_pdev_to_mapping(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) if (!map)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) if (map->is_suspended)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) map->is_suspended = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) /* Save all window configs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) for (i = 0; i < STA2X11_NR_FUNCS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) struct sta2x11_ahb_regs *regs = map->regs + i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) pci_read_config_dword(pdev, AHB_BASE(i), ®s->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) pci_read_config_dword(pdev, AHB_PEXLBASE(i), ®s->pexlbase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) pci_read_config_dword(pdev, AHB_PEXHBASE(i), ®s->pexhbase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) pci_read_config_dword(pdev, AHB_CRW(i), ®s->crw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) DECLARE_PCI_FIXUP_SUSPEND(PCI_VENDOR_ID_STMICRO, PCI_ANY_ID, suspend_mapping);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) static void resume_mapping(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) struct sta2x11_mapping *map = sta2x11_pdev_to_mapping(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) if (!map)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) if (!map->is_suspended)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) map->is_suspended = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) /* Restore all window configs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) for (i = 0; i < STA2X11_NR_FUNCS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) struct sta2x11_ahb_regs *regs = map->regs + i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) pci_write_config_dword(pdev, AHB_BASE(i), regs->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) pci_write_config_dword(pdev, AHB_PEXLBASE(i), regs->pexlbase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) pci_write_config_dword(pdev, AHB_PEXHBASE(i), regs->pexhbase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) pci_write_config_dword(pdev, AHB_CRW(i), regs->crw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) pci_set_master(pdev); /* Like at boot, enable master on all devices */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_STMICRO, PCI_ANY_ID, resume_mapping);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #endif /* CONFIG_PM */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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