^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * mmconfig-shared.c - Low-level direct PCI config space access via
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * MMCONFIG - common code between i386 and x86-64.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * This code does:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * - known chipset handling
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * - ACPI decoding and validation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Per-architecture code takes care of the mappings and accesses
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * themselves.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/sfi_acpi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/bitmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/dmi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/mutex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/rculist.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <asm/e820/api.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <asm/pci_x86.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <asm/acpi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define PREFIX "PCI: "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) /* Indicate if the mmcfg resources have been placed into the resource table. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) static bool pci_mmcfg_running_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) static bool pci_mmcfg_arch_init_failed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) static DEFINE_MUTEX(pci_mmcfg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define pci_mmcfg_lock_held() lock_is_held(&(pci_mmcfg_lock).dep_map)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) LIST_HEAD(pci_mmcfg_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) static void __init pci_mmconfig_remove(struct pci_mmcfg_region *cfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) if (cfg->res.parent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) release_resource(&cfg->res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) list_del(&cfg->list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) kfree(cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) static void __init free_all_mmcfg(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) struct pci_mmcfg_region *cfg, *tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) pci_mmcfg_arch_free();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) list_for_each_entry_safe(cfg, tmp, &pci_mmcfg_list, list)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) pci_mmconfig_remove(cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) static void list_add_sorted(struct pci_mmcfg_region *new)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) struct pci_mmcfg_region *cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) /* keep list sorted by segment and starting bus number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) list_for_each_entry_rcu(cfg, &pci_mmcfg_list, list, pci_mmcfg_lock_held()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) if (cfg->segment > new->segment ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) (cfg->segment == new->segment &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) cfg->start_bus >= new->start_bus)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) list_add_tail_rcu(&new->list, &cfg->list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) list_add_tail_rcu(&new->list, &pci_mmcfg_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) static struct pci_mmcfg_region *pci_mmconfig_alloc(int segment, int start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) int end, u64 addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) struct pci_mmcfg_region *new;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) if (addr == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) new = kzalloc(sizeof(*new), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) if (!new)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) new->address = addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) new->segment = segment;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) new->start_bus = start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) new->end_bus = end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) res = &new->res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) res->start = addr + PCI_MMCFG_BUS_OFFSET(start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) res->end = addr + PCI_MMCFG_BUS_OFFSET(end + 1) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) res->flags = IORESOURCE_MEM | IORESOURCE_BUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) snprintf(new->name, PCI_MMCFG_RESOURCE_NAME_LEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) "PCI MMCONFIG %04x [bus %02x-%02x]", segment, start, end);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) res->name = new->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) return new;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) struct pci_mmcfg_region *__init pci_mmconfig_add(int segment, int start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) int end, u64 addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) struct pci_mmcfg_region *new;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) new = pci_mmconfig_alloc(segment, start, end, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) if (new) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) mutex_lock(&pci_mmcfg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) list_add_sorted(new);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) mutex_unlock(&pci_mmcfg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) pr_info(PREFIX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) "MMCONFIG for domain %04x [bus %02x-%02x] at %pR "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) "(base %#lx)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) segment, start, end, &new->res, (unsigned long)addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) return new;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) struct pci_mmcfg_region *pci_mmconfig_lookup(int segment, int bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) struct pci_mmcfg_region *cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) list_for_each_entry_rcu(cfg, &pci_mmcfg_list, list, pci_mmcfg_lock_held())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) if (cfg->segment == segment &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) cfg->start_bus <= bus && bus <= cfg->end_bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) return cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) static const char *__init pci_mmcfg_e7520(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) u32 win;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) raw_pci_ops->read(0, 0, PCI_DEVFN(0, 0), 0xce, 2, &win);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) win = win & 0xf000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) if (win == 0x0000 || win == 0xf000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) if (pci_mmconfig_add(0, 0, 255, win << 16) == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) return "Intel Corporation E7520 Memory Controller Hub";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) static const char *__init pci_mmcfg_intel_945(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) u32 pciexbar, mask = 0, len = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) raw_pci_ops->read(0, 0, PCI_DEVFN(0, 0), 0x48, 4, &pciexbar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) /* Enable bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) if (!(pciexbar & 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) /* Size bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) switch ((pciexbar >> 1) & 3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) mask = 0xf0000000U;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) len = 0x10000000U;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) mask = 0xf8000000U;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) len = 0x08000000U;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) mask = 0xfc000000U;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) len = 0x04000000U;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) /* Errata #2, things break when not aligned on a 256Mb boundary */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) /* Can only happen in 64M/128M mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) if ((pciexbar & mask) & 0x0fffffffU)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) /* Don't hit the APIC registers and their friends */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) if ((pciexbar & mask) >= 0xf0000000U)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) if (pci_mmconfig_add(0, 0, (len >> 20) - 1, pciexbar & mask) == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) return "Intel Corporation 945G/GZ/P/PL Express Memory Controller Hub";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) static const char *__init pci_mmcfg_amd_fam10h(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) u32 low, high, address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) u64 base, msr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) unsigned segnbits = 0, busnbits, end_bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) if (!(pci_probe & PCI_CHECK_ENABLE_AMD_MMCONF))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) address = MSR_FAM10H_MMIO_CONF_BASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) if (rdmsr_safe(address, &low, &high))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) msr = high;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) msr <<= 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) msr |= low;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) /* mmconfig is not enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) if (!(msr & FAM10H_MMIO_CONF_ENABLE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) base = msr & (FAM10H_MMIO_CONF_BASE_MASK<<FAM10H_MMIO_CONF_BASE_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) busnbits = (msr >> FAM10H_MMIO_CONF_BUSRANGE_SHIFT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) FAM10H_MMIO_CONF_BUSRANGE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) * only handle bus 0 ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) * need to skip it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) if (!busnbits)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) if (busnbits > 8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) segnbits = busnbits - 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) busnbits = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) end_bus = (1 << busnbits) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) for (i = 0; i < (1 << segnbits); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) if (pci_mmconfig_add(i, 0, end_bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) base + (1<<28) * i) == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) free_all_mmcfg();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) return "AMD Family 10h NB";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) static bool __initdata mcp55_checked;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) static const char *__init pci_mmcfg_nvidia_mcp55(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) int bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) int mcp55_mmconf_found = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) static const u32 extcfg_regnum __initconst = 0x90;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) static const u32 extcfg_regsize __initconst = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) static const u32 extcfg_enable_mask __initconst = 1 << 31;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) static const u32 extcfg_start_mask __initconst = 0xff << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) static const int extcfg_start_shift __initconst = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) static const u32 extcfg_size_mask __initconst = 0x3 << 28;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) static const int extcfg_size_shift __initconst = 28;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) static const int extcfg_sizebus[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 0x100, 0x80, 0x40, 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) static const u32 extcfg_base_mask[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 0x7ff8, 0x7ffc, 0x7ffe, 0x7fff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) static const int extcfg_base_lshift __initconst = 25;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) * do check if amd fam10h already took over
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) if (!acpi_disabled || !list_empty(&pci_mmcfg_list) || mcp55_checked)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) mcp55_checked = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) for (bus = 0; bus < 256; bus++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) u64 base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) u32 l, extcfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) u16 vendor, device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) int start, size_index, end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) raw_pci_ops->read(0, bus, PCI_DEVFN(0, 0), 0, 4, &l);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) vendor = l & 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) device = (l >> 16) & 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) if (PCI_VENDOR_ID_NVIDIA != vendor || 0x0369 != device)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) raw_pci_ops->read(0, bus, PCI_DEVFN(0, 0), extcfg_regnum,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) extcfg_regsize, &extcfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) if (!(extcfg & extcfg_enable_mask))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) size_index = (extcfg & extcfg_size_mask) >> extcfg_size_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) base = extcfg & extcfg_base_mask[size_index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) /* base could > 4G */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) base <<= extcfg_base_lshift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) start = (extcfg & extcfg_start_mask) >> extcfg_start_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) end = start + extcfg_sizebus[size_index] - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) if (pci_mmconfig_add(0, start, end, base) == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) mcp55_mmconf_found++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) if (!mcp55_mmconf_found)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) return "nVidia MCP55";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) struct pci_mmcfg_hostbridge_probe {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) u32 bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) u32 devfn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) u32 vendor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) u32 device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) const char *(*probe)(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) static const struct pci_mmcfg_hostbridge_probe pci_mmcfg_probes[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) { 0, PCI_DEVFN(0, 0), PCI_VENDOR_ID_INTEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) PCI_DEVICE_ID_INTEL_E7520_MCH, pci_mmcfg_e7520 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) { 0, PCI_DEVFN(0, 0), PCI_VENDOR_ID_INTEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) PCI_DEVICE_ID_INTEL_82945G_HB, pci_mmcfg_intel_945 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) { 0, PCI_DEVFN(0x18, 0), PCI_VENDOR_ID_AMD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 0x1200, pci_mmcfg_amd_fam10h },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) { 0xff, PCI_DEVFN(0, 0), PCI_VENDOR_ID_AMD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 0x1200, pci_mmcfg_amd_fam10h },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) { 0, PCI_DEVFN(0, 0), PCI_VENDOR_ID_NVIDIA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 0x0369, pci_mmcfg_nvidia_mcp55 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) static void __init pci_mmcfg_check_end_bus_number(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) struct pci_mmcfg_region *cfg, *cfgx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) /* Fixup overlaps */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) list_for_each_entry(cfg, &pci_mmcfg_list, list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) if (cfg->end_bus < cfg->start_bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) cfg->end_bus = 255;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) /* Don't access the list head ! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) if (cfg->list.next == &pci_mmcfg_list)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) cfgx = list_entry(cfg->list.next, typeof(*cfg), list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) if (cfg->end_bus >= cfgx->start_bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) cfg->end_bus = cfgx->start_bus - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) static int __init pci_mmcfg_check_hostbridge(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) u32 l;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) u32 bus, devfn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) u16 vendor, device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) if (!raw_pci_ops)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) free_all_mmcfg();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) for (i = 0; i < ARRAY_SIZE(pci_mmcfg_probes); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) bus = pci_mmcfg_probes[i].bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) devfn = pci_mmcfg_probes[i].devfn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) raw_pci_ops->read(0, bus, devfn, 0, 4, &l);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) vendor = l & 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) device = (l >> 16) & 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) name = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) if (pci_mmcfg_probes[i].vendor == vendor &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) pci_mmcfg_probes[i].device == device)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) name = pci_mmcfg_probes[i].probe();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) if (name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) pr_info(PREFIX "%s with MMCONFIG support\n", name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) /* some end_bus_number is crazy, fix it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) pci_mmcfg_check_end_bus_number();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) return !list_empty(&pci_mmcfg_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) static acpi_status check_mcfg_resource(struct acpi_resource *res, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) struct resource *mcfg_res = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) struct acpi_resource_address64 address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) acpi_status status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) if (res->type == ACPI_RESOURCE_TYPE_FIXED_MEMORY32) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) struct acpi_resource_fixed_memory32 *fixmem32 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) &res->data.fixed_memory32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) if (!fixmem32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) return AE_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) if ((mcfg_res->start >= fixmem32->address) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) (mcfg_res->end < (fixmem32->address +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) fixmem32->address_length))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) mcfg_res->flags = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) return AE_CTRL_TERMINATE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) if ((res->type != ACPI_RESOURCE_TYPE_ADDRESS32) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) (res->type != ACPI_RESOURCE_TYPE_ADDRESS64))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) return AE_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) status = acpi_resource_to_address64(res, &address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) if (ACPI_FAILURE(status) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) (address.address.address_length <= 0) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) (address.resource_type != ACPI_MEMORY_RANGE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) return AE_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) if ((mcfg_res->start >= address.address.minimum) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) (mcfg_res->end < (address.address.minimum + address.address.address_length))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) mcfg_res->flags = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) return AE_CTRL_TERMINATE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) return AE_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) static acpi_status find_mboard_resource(acpi_handle handle, u32 lvl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) void *context, void **rv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) struct resource *mcfg_res = context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) acpi_walk_resources(handle, METHOD_NAME__CRS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) check_mcfg_resource, context);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) if (mcfg_res->flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) return AE_CTRL_TERMINATE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) return AE_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) static bool is_acpi_reserved(u64 start, u64 end, enum e820_type not_used)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) struct resource mcfg_res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) mcfg_res.start = start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) mcfg_res.end = end - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) mcfg_res.flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) acpi_get_devices("PNP0C01", find_mboard_resource, &mcfg_res, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) if (!mcfg_res.flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) acpi_get_devices("PNP0C02", find_mboard_resource, &mcfg_res,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) return mcfg_res.flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) typedef bool (*check_reserved_t)(u64 start, u64 end, enum e820_type type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) static bool __ref is_mmconf_reserved(check_reserved_t is_reserved,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) struct pci_mmcfg_region *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) struct device *dev, int with_e820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) u64 addr = cfg->res.start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) u64 size = resource_size(&cfg->res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) u64 old_size = size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) int num_buses;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) char *method = with_e820 ? "E820" : "ACPI motherboard resources";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) while (!is_reserved(addr, addr + size, E820_TYPE_RESERVED)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) size >>= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) if (size < (16UL<<20))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) if (size < (16UL<<20) && size != old_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) if (dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) dev_info(dev, "MMCONFIG at %pR reserved in %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) &cfg->res, method);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) pr_info(PREFIX "MMCONFIG at %pR reserved in %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) &cfg->res, method);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) if (old_size != size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) /* update end_bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) cfg->end_bus = cfg->start_bus + ((size>>20) - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) num_buses = cfg->end_bus - cfg->start_bus + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) cfg->res.end = cfg->res.start +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) PCI_MMCFG_BUS_OFFSET(num_buses) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) snprintf(cfg->name, PCI_MMCFG_RESOURCE_NAME_LEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) "PCI MMCONFIG %04x [bus %02x-%02x]",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) cfg->segment, cfg->start_bus, cfg->end_bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) if (dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) dev_info(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) "MMCONFIG "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) "at %pR (base %#lx) (size reduced!)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) &cfg->res, (unsigned long) cfg->address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) pr_info(PREFIX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) "MMCONFIG for %04x [bus%02x-%02x] "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) "at %pR (base %#lx) (size reduced!)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) cfg->segment, cfg->start_bus, cfg->end_bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) &cfg->res, (unsigned long) cfg->address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) static bool __ref
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) pci_mmcfg_check_reserved(struct device *dev, struct pci_mmcfg_region *cfg, int early)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) if (!early && !acpi_disabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) if (is_mmconf_reserved(is_acpi_reserved, cfg, dev, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) if (dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) dev_info(dev, FW_INFO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) "MMCONFIG at %pR not reserved in "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) "ACPI motherboard resources\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) &cfg->res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) pr_info(FW_INFO PREFIX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) "MMCONFIG at %pR not reserved in "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) "ACPI motherboard resources\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) &cfg->res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) * e820__mapped_all() is marked as __init.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) * All entries from ACPI MCFG table have been checked at boot time.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) * For MCFG information constructed from hotpluggable host bridge's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) * _CBA method, just assume it's reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) if (pci_mmcfg_running_state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) /* Don't try to do this check unless configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) type 1 is available. how about type 2 ?*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) if (raw_pci_ops)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) return is_mmconf_reserved(e820__mapped_all, cfg, dev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) static void __init pci_mmcfg_reject_broken(int early)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) struct pci_mmcfg_region *cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) list_for_each_entry(cfg, &pci_mmcfg_list, list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) if (pci_mmcfg_check_reserved(NULL, cfg, early) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) pr_info(PREFIX "not using MMCONFIG\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) free_all_mmcfg();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) static int __init acpi_mcfg_check_entry(struct acpi_table_mcfg *mcfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) struct acpi_mcfg_allocation *cfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) if (cfg->address < 0xFFFFFFFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) if (!strncmp(mcfg->header.oem_id, "SGI", 3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) if ((mcfg->header.revision >= 1) && (dmi_get_bios_year() >= 2010))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) pr_err(PREFIX "MCFG region for %04x [bus %02x-%02x] at %#llx "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) "is above 4GB, ignored\n", cfg->pci_segment,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) cfg->start_bus_number, cfg->end_bus_number, cfg->address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) static int __init pci_parse_mcfg(struct acpi_table_header *header)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) struct acpi_table_mcfg *mcfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) struct acpi_mcfg_allocation *cfg_table, *cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) unsigned long i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) int entries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) if (!header)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) mcfg = (struct acpi_table_mcfg *)header;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) /* how many config structures do we have */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) free_all_mmcfg();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) entries = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) i = header->length - sizeof(struct acpi_table_mcfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) while (i >= sizeof(struct acpi_mcfg_allocation)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) entries++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) i -= sizeof(struct acpi_mcfg_allocation);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) if (entries == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) pr_err(PREFIX "MMCONFIG has no entries\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) cfg_table = (struct acpi_mcfg_allocation *) &mcfg[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) for (i = 0; i < entries; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) cfg = &cfg_table[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) if (acpi_mcfg_check_entry(mcfg, cfg)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) free_all_mmcfg();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) if (pci_mmconfig_add(cfg->pci_segment, cfg->start_bus_number,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) cfg->end_bus_number, cfg->address) == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) pr_warn(PREFIX "no memory for MCFG entries\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) free_all_mmcfg();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) #ifdef CONFIG_ACPI_APEI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) extern int (*arch_apei_filter_addr)(int (*func)(__u64 start, __u64 size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) void *data), void *data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) static int pci_mmcfg_for_each_region(int (*func)(__u64 start, __u64 size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) void *data), void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) struct pci_mmcfg_region *cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) if (list_empty(&pci_mmcfg_list))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) list_for_each_entry(cfg, &pci_mmcfg_list, list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) rc = func(cfg->res.start, resource_size(&cfg->res), data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) #define set_apei_filter() (arch_apei_filter_addr = pci_mmcfg_for_each_region)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) #define set_apei_filter()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) static void __init __pci_mmcfg_init(int early)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) pci_mmcfg_reject_broken(early);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) if (list_empty(&pci_mmcfg_list))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) if (pcibios_last_bus < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) const struct pci_mmcfg_region *cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) list_for_each_entry(cfg, &pci_mmcfg_list, list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) if (cfg->segment)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) pcibios_last_bus = cfg->end_bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) if (pci_mmcfg_arch_init())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) pci_probe = (pci_probe & ~PCI_PROBE_MASK) | PCI_PROBE_MMCONF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) free_all_mmcfg();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) pci_mmcfg_arch_init_failed = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) static int __initdata known_bridge;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) void __init pci_mmcfg_early_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) if (pci_probe & PCI_PROBE_MMCONF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) if (pci_mmcfg_check_hostbridge())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) known_bridge = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) acpi_sfi_table_parse(ACPI_SIG_MCFG, pci_parse_mcfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) __pci_mmcfg_init(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) set_apei_filter();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) void __init pci_mmcfg_late_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) /* MMCONFIG disabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) if ((pci_probe & PCI_PROBE_MMCONF) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) if (known_bridge)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) /* MMCONFIG hasn't been enabled yet, try again */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) if (pci_probe & PCI_PROBE_MASK & ~PCI_PROBE_MMCONF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) acpi_sfi_table_parse(ACPI_SIG_MCFG, pci_parse_mcfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) __pci_mmcfg_init(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) static int __init pci_mmcfg_late_insert_resources(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) struct pci_mmcfg_region *cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) pci_mmcfg_running_state = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) /* If we are not using MMCONFIG, don't insert the resources. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) if ((pci_probe & PCI_PROBE_MMCONF) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) * Attempt to insert the mmcfg resources but not with the busy flag
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) * marked so it won't cause request errors when __request_region is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) * called.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) list_for_each_entry(cfg, &pci_mmcfg_list, list)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) if (!cfg->res.parent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) insert_resource(&iomem_resource, &cfg->res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) * Perform MMCONFIG resource insertion after PCI initialization to allow for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) * misprogrammed MCFG tables that state larger sizes but actually conflict
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) * with other system resources.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) late_initcall(pci_mmcfg_late_insert_resources);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) /* Add MMCFG information for host bridges */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) int pci_mmconfig_insert(struct device *dev, u16 seg, u8 start, u8 end,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) phys_addr_t addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) struct resource *tmp = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) struct pci_mmcfg_region *cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) if (!(pci_probe & PCI_PROBE_MMCONF) || pci_mmcfg_arch_init_failed)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) if (start > end)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) mutex_lock(&pci_mmcfg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) cfg = pci_mmconfig_lookup(seg, start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) if (cfg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) if (cfg->end_bus < end)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) dev_info(dev, FW_INFO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) "MMCONFIG for "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) "domain %04x [bus %02x-%02x] "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) "only partially covers this bridge\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) cfg->segment, cfg->start_bus, cfg->end_bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) mutex_unlock(&pci_mmcfg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) return -EEXIST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) if (!addr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) mutex_unlock(&pci_mmcfg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) rc = -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) cfg = pci_mmconfig_alloc(seg, start, end, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) if (cfg == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) dev_warn(dev, "fail to add MMCONFIG (out of memory)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) rc = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) } else if (!pci_mmcfg_check_reserved(dev, cfg, 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) dev_warn(dev, FW_BUG "MMCONFIG %pR isn't reserved\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) &cfg->res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) /* Insert resource if it's not in boot stage */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) if (pci_mmcfg_running_state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) tmp = insert_resource_conflict(&iomem_resource,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) &cfg->res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) if (tmp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) dev_warn(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) "MMCONFIG %pR conflicts with "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) "%s %pR\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) &cfg->res, tmp->name, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) } else if (pci_mmcfg_arch_map(cfg)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) dev_warn(dev, "fail to map MMCONFIG %pR.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) &cfg->res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) list_add_sorted(cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) dev_info(dev, "MMCONFIG at %pR (base %#lx)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) &cfg->res, (unsigned long)addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) cfg = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) rc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) if (cfg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) if (cfg->res.parent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) release_resource(&cfg->res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) kfree(cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) mutex_unlock(&pci_mmcfg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) /* Delete MMCFG information for host bridges */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) int pci_mmconfig_delete(u16 seg, u8 start, u8 end)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) struct pci_mmcfg_region *cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) mutex_lock(&pci_mmcfg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) list_for_each_entry_rcu(cfg, &pci_mmcfg_list, list)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) if (cfg->segment == seg && cfg->start_bus == start &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) cfg->end_bus == end) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) list_del_rcu(&cfg->list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) synchronize_rcu();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) pci_mmcfg_arch_unmap(cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) if (cfg->res.parent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) release_resource(&cfg->res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) mutex_unlock(&pci_mmcfg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) kfree(cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) mutex_unlock(&pci_mmcfg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) return -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags