^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Low-Level PCI Support for PC -- Routing of Interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * (c) 1999--2000 Martin Mares <mj@ucw.cz>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/dmi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/smp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <asm/io_apic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/acpi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <asm/pci_x86.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define PIRQ_SIGNATURE (('$' << 0) + ('P' << 8) + ('I' << 16) + ('R' << 24))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define PIRQ_VERSION 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) static int broken_hp_bios_irq9;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) static int acer_tm360_irqrouting;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) static struct irq_routing_table *pirq_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) static int pirq_enable_irq(struct pci_dev *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) static void pirq_disable_irq(struct pci_dev *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * Never use: 0, 1, 2 (timer, keyboard, and cascade)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * Avoid using: 13, 14 and 15 (FP error and IDE).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * Penalize: 3, 4, 6, 7, 12 (known ISA uses: serial, floppy, parallel and mouse)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) unsigned int pcibios_irq_mask = 0xfff8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) static int pirq_penalty[16] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 1000000, 1000000, 1000000, 1000, 1000, 0, 1000, 1000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 0, 0, 0, 0, 1000, 100000, 100000, 100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) struct irq_router {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) u16 vendor, device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) int (*get)(struct pci_dev *router, struct pci_dev *dev, int pirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) int (*set)(struct pci_dev *router, struct pci_dev *dev, int pirq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) int new);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) struct irq_router_handler {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) u16 vendor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) int (*probe)(struct irq_router *r, struct pci_dev *router, u16 device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) int (*pcibios_enable_irq)(struct pci_dev *dev) = pirq_enable_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) void (*pcibios_disable_irq)(struct pci_dev *dev) = pirq_disable_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * Check passed address for the PCI IRQ Routing Table signature
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * and perform checksum verification.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) static inline struct irq_routing_table *pirq_check_routing_table(u8 *addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) struct irq_routing_table *rt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) u8 sum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) rt = (struct irq_routing_table *) addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) if (rt->signature != PIRQ_SIGNATURE ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) rt->version != PIRQ_VERSION ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) rt->size % 16 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) rt->size < sizeof(struct irq_routing_table))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) sum = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) for (i = 0; i < rt->size; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) sum += addr[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) if (!sum) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) DBG(KERN_DEBUG "PCI: Interrupt Routing Table found at 0x%p\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) rt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) return rt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) * Search 0xf0000 -- 0xfffff for the PCI IRQ Routing Table.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) static struct irq_routing_table * __init pirq_find_routing_table(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) u8 *addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) struct irq_routing_table *rt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) if (pirq_table_addr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) rt = pirq_check_routing_table((u8 *) __va(pirq_table_addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) if (rt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) return rt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) printk(KERN_WARNING "PCI: PIRQ table NOT found at pirqaddr\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) for (addr = (u8 *) __va(0xf0000); addr < (u8 *) __va(0x100000); addr += 16) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) rt = pirq_check_routing_table(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) if (rt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) return rt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) * If we have a IRQ routing table, use it to search for peer host
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) * bridges. It's a gross hack, but since there are no other known
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) * ways how to get a list of buses, we have to go this way.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) static void __init pirq_peer_trick(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) struct irq_routing_table *rt = pirq_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) u8 busmap[256];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) struct irq_info *e;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) memset(busmap, 0, sizeof(busmap));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) for (i = 0; i < (rt->size - sizeof(struct irq_routing_table)) / sizeof(struct irq_info); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) e = &rt->slots[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #ifdef DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) int j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) DBG(KERN_DEBUG "%02x:%02x slot=%02x", e->bus, e->devfn/8, e->slot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) for (j = 0; j < 4; j++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) DBG(" %d:%02x/%04x", j, e->irq[j].link, e->irq[j].bitmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) DBG("\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) busmap[e->bus] = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) for (i = 1; i < 256; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) if (!busmap[i] || pci_find_bus(0, i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) pcibios_scan_root(i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) pcibios_last_bus = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) * Code for querying and setting of IRQ routes on various interrupt routers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) * PIC Edge/Level Control Registers (ELCR) 0x4d0 & 0x4d1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) void elcr_set_level_irq(unsigned int irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) unsigned char mask = 1 << (irq & 7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) unsigned int port = 0x4d0 + (irq >> 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) unsigned char val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) static u16 elcr_irq_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) if (irq >= 16 || (1 << irq) & elcr_irq_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) elcr_irq_mask |= (1 << irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) printk(KERN_DEBUG "PCI: setting IRQ %u as level-triggered\n", irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) val = inb(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) if (!(val & mask)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) DBG(KERN_DEBUG " -> edge");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) outb(val | mask, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) * Common IRQ routing practice: nibbles in config space,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) * offset by some magic constant.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) static unsigned int read_config_nybble(struct pci_dev *router, unsigned offset, unsigned nr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) u8 x;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) unsigned reg = offset + (nr >> 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) pci_read_config_byte(router, reg, &x);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) return (nr & 1) ? (x >> 4) : (x & 0xf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) static void write_config_nybble(struct pci_dev *router, unsigned offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) unsigned nr, unsigned int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) u8 x;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) unsigned reg = offset + (nr >> 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) pci_read_config_byte(router, reg, &x);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) x = (nr & 1) ? ((x & 0x0f) | (val << 4)) : ((x & 0xf0) | val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) pci_write_config_byte(router, reg, x);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) * ALI pirq entries are damn ugly, and completely undocumented.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) * This has been figured out from pirq tables, and it's not a pretty
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) * picture.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) static int pirq_ali_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) static const unsigned char irqmap[16] = { 0, 9, 3, 10, 4, 5, 7, 6, 1, 11, 0, 12, 0, 14, 0, 15 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) WARN_ON_ONCE(pirq > 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) return irqmap[read_config_nybble(router, 0x48, pirq-1)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) static int pirq_ali_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) static const unsigned char irqmap[16] = { 0, 8, 0, 2, 4, 5, 7, 6, 0, 1, 3, 9, 11, 0, 13, 15 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) unsigned int val = irqmap[irq];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) WARN_ON_ONCE(pirq > 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) if (val) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) write_config_nybble(router, 0x48, pirq-1, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) * The Intel PIIX4 pirq rules are fairly simple: "pirq" is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) * just a pointer to the config space.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) static int pirq_piix_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) u8 x;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) pci_read_config_byte(router, pirq, &x);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) return (x < 16) ? x : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) static int pirq_piix_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) pci_write_config_byte(router, pirq, irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) * The VIA pirq rules are nibble-based, like ALI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) * but without the ugly irq number munging.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) * However, PIRQD is in the upper instead of lower 4 bits.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) static int pirq_via_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) return read_config_nybble(router, 0x55, pirq == 4 ? 5 : pirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) static int pirq_via_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) write_config_nybble(router, 0x55, pirq == 4 ? 5 : pirq, irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) * The VIA pirq rules are nibble-based, like ALI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) * but without the ugly irq number munging.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) * However, for 82C586, nibble map is different .
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) static int pirq_via586_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) static const unsigned int pirqmap[5] = { 3, 2, 5, 1, 1 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) WARN_ON_ONCE(pirq > 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) return read_config_nybble(router, 0x55, pirqmap[pirq-1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) static int pirq_via586_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) static const unsigned int pirqmap[5] = { 3, 2, 5, 1, 1 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) WARN_ON_ONCE(pirq > 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) write_config_nybble(router, 0x55, pirqmap[pirq-1], irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) * ITE 8330G pirq rules are nibble-based
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) * FIXME: pirqmap may be { 1, 0, 3, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) * 2+3 are both mapped to irq 9 on my system
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) static int pirq_ite_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) static const unsigned char pirqmap[4] = { 1, 0, 2, 3 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) WARN_ON_ONCE(pirq > 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) return read_config_nybble(router, 0x43, pirqmap[pirq-1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) static int pirq_ite_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) static const unsigned char pirqmap[4] = { 1, 0, 2, 3 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) WARN_ON_ONCE(pirq > 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) write_config_nybble(router, 0x43, pirqmap[pirq-1], irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) * OPTI: high four bits are nibble pointer..
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) * I wonder what the low bits do?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) static int pirq_opti_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) return read_config_nybble(router, 0xb8, pirq >> 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) static int pirq_opti_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) write_config_nybble(router, 0xb8, pirq >> 4, irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) * Cyrix: nibble offset 0x5C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) * 0x5C bits 7:4 is INTB bits 3:0 is INTA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) * 0x5D bits 7:4 is INTD bits 3:0 is INTC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) static int pirq_cyrix_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) return read_config_nybble(router, 0x5C, (pirq-1)^1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) static int pirq_cyrix_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) write_config_nybble(router, 0x5C, (pirq-1)^1, irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) * PIRQ routing for SiS 85C503 router used in several SiS chipsets.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) * We have to deal with the following issues here:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) * - vendors have different ideas about the meaning of link values
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) * - some onboard devices (integrated in the chipset) have special
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) * links and are thus routed differently (i.e. not via PCI INTA-INTD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) * - different revision of the router have a different layout for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) * the routing registers, particularly for the onchip devices
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) * For all routing registers the common thing is we have one byte
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) * per routeable link which is defined as:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) * bit 7 IRQ mapping enabled (0) or disabled (1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) * bits [6:4] reserved (sometimes used for onchip devices)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) * bits [3:0] IRQ to map to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) * allowed: 3-7, 9-12, 14-15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) * reserved: 0, 1, 2, 8, 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) * The config-space registers located at 0x41/0x42/0x43/0x44 are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) * always used to route the normal PCI INT A/B/C/D respectively.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) * Apparently there are systems implementing PCI routing table using
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) * link values 0x01-0x04 and others using 0x41-0x44 for PCI INTA..D.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) * We try our best to handle both link mappings.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) * Currently (2003-05-21) it appears most SiS chipsets follow the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) * definition of routing registers from the SiS-5595 southbridge.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) * According to the SiS 5595 datasheets the revision id's of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) * router (ISA-bridge) should be 0x01 or 0xb0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) * Furthermore we've also seen lspci dumps with revision 0x00 and 0xb1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) * Looks like these are used in a number of SiS 5xx/6xx/7xx chipsets.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) * They seem to work with the current routing code. However there is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) * some concern because of the two USB-OHCI HCs (original SiS 5595
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) * had only one). YMMV.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) * Onchip routing for router rev-id 0x01/0xb0 and probably 0x00/0xb1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) * 0x61: IDEIRQ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) * bits [6:5] must be written 01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) * bit 4 channel-select primary (0), secondary (1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) * 0x62: USBIRQ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) * bit 6 OHCI function disabled (0), enabled (1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) * 0x6a: ACPI/SCI IRQ: bits 4-6 reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) * 0x7e: Data Acq. Module IRQ - bits 4-6 reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) * We support USBIRQ (in addition to INTA-INTD) and keep the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) * IDE, ACPI and DAQ routing untouched as set by the BIOS.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) * Currently the only reported exception is the new SiS 65x chipset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) * which includes the SiS 69x southbridge. Here we have the 85C503
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) * router revision 0x04 and there are changes in the register layout
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) * mostly related to the different USB HCs with USB 2.0 support.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) * Onchip routing for router rev-id 0x04 (try-and-error observation)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) * 0x60/0x61/0x62/0x63: 1xEHCI and 3xOHCI (companion) USB-HCs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) * bit 6-4 are probably unused, not like 5595
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) #define PIRQ_SIS_IRQ_MASK 0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) #define PIRQ_SIS_IRQ_DISABLE 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) #define PIRQ_SIS_USB_ENABLE 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) static int pirq_sis_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) u8 x;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) int reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) reg = pirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) if (reg >= 0x01 && reg <= 0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) reg += 0x40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) pci_read_config_byte(router, reg, &x);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) return (x & PIRQ_SIS_IRQ_DISABLE) ? 0 : (x & PIRQ_SIS_IRQ_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) static int pirq_sis_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) u8 x;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) int reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) reg = pirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) if (reg >= 0x01 && reg <= 0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) reg += 0x40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) pci_read_config_byte(router, reg, &x);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) x &= ~(PIRQ_SIS_IRQ_MASK | PIRQ_SIS_IRQ_DISABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) x |= irq ? irq: PIRQ_SIS_IRQ_DISABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) pci_write_config_byte(router, reg, x);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) * VLSI: nibble offset 0x74 - educated guess due to routing table and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) * config space of VLSI 82C534 PCI-bridge/router (1004:0102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) * Tested on HP OmniBook 800 covering PIRQ 1, 2, 4, 8 for onboard
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) * devices, PIRQ 3 for non-pci(!) soundchip and (untested) PIRQ 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) * for the busbridge to the docking station.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) static int pirq_vlsi_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) WARN_ON_ONCE(pirq >= 9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) if (pirq > 8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) dev_info(&dev->dev, "VLSI router PIRQ escape (%d)\n", pirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) return read_config_nybble(router, 0x74, pirq-1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) static int pirq_vlsi_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) WARN_ON_ONCE(pirq >= 9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) if (pirq > 8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) dev_info(&dev->dev, "VLSI router PIRQ escape (%d)\n", pirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) write_config_nybble(router, 0x74, pirq-1, irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) * ServerWorks: PCI interrupts mapped to system IRQ lines through Index
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) * and Redirect I/O registers (0x0c00 and 0x0c01). The Index register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) * format is (PCIIRQ## | 0x10), e.g.: PCIIRQ10=0x1a. The Redirect
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) * register is a straight binary coding of desired PIC IRQ (low nibble).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) * The 'link' value in the PIRQ table is already in the correct format
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) * for the Index register. There are some special index values:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) * 0x00 for ACPI (SCI), 0x01 for USB, 0x02 for IDE0, 0x04 for IDE1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) * and 0x03 for SMBus.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) static int pirq_serverworks_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) outb(pirq, 0xc00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) return inb(0xc01) & 0xf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) static int pirq_serverworks_set(struct pci_dev *router, struct pci_dev *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) int pirq, int irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) outb(pirq, 0xc00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) outb(irq, 0xc01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) /* Support for AMD756 PCI IRQ Routing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) * Jhon H. Caicedo <jhcaiced@osso.org.co>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) * Jun/21/2001 0.2.0 Release, fixed to use "nybble" functions... (jhcaiced)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) * Jun/19/2001 Alpha Release 0.1.0 (jhcaiced)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) * The AMD756 pirq rules are nibble-based
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) * offset 0x56 0-3 PIRQA 4-7 PIRQB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) * offset 0x57 0-3 PIRQC 4-7 PIRQD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) static int pirq_amd756_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) u8 irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) irq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) if (pirq <= 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) irq = read_config_nybble(router, 0x56, pirq - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) dev_info(&dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) "AMD756: dev [%04x:%04x], router PIRQ %d get IRQ %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) dev->vendor, dev->device, pirq, irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) return irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) static int pirq_amd756_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) dev_info(&dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) "AMD756: dev [%04x:%04x], router PIRQ %d set IRQ %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) dev->vendor, dev->device, pirq, irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) if (pirq <= 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) write_config_nybble(router, 0x56, pirq - 1, irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) * PicoPower PT86C523
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) static int pirq_pico_get(struct pci_dev *router, struct pci_dev *dev, int pirq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) outb(0x10 + ((pirq - 1) >> 1), 0x24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) return ((pirq - 1) & 1) ? (inb(0x26) >> 4) : (inb(0x26) & 0xf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) static int pirq_pico_set(struct pci_dev *router, struct pci_dev *dev, int pirq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) int irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) unsigned int x;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) outb(0x10 + ((pirq - 1) >> 1), 0x24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) x = inb(0x26);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) x = ((pirq - 1) & 1) ? ((x & 0x0f) | (irq << 4)) : ((x & 0xf0) | (irq));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) outb(x, 0x26);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) #ifdef CONFIG_PCI_BIOS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) static int pirq_bios_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) struct pci_dev *bridge;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) int pin = pci_get_interrupt_pin(dev, &bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) return pcibios_set_irq_routing(bridge, pin - 1, irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) static __init int intel_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) static struct pci_device_id __initdata pirq_440gx[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443GX_0) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443GX_2) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) /* 440GX has a proprietary PIRQ router -- don't use it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) if (pci_dev_present(pirq_440gx))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) switch (device) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) case PCI_DEVICE_ID_INTEL_82371FB_0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) case PCI_DEVICE_ID_INTEL_82371SB_0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) case PCI_DEVICE_ID_INTEL_82371AB_0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) case PCI_DEVICE_ID_INTEL_82371MX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) case PCI_DEVICE_ID_INTEL_82443MX_0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) case PCI_DEVICE_ID_INTEL_82801AA_0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) case PCI_DEVICE_ID_INTEL_82801AB_0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) case PCI_DEVICE_ID_INTEL_82801BA_0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) case PCI_DEVICE_ID_INTEL_82801BA_10:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) case PCI_DEVICE_ID_INTEL_82801CA_0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) case PCI_DEVICE_ID_INTEL_82801CA_12:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) case PCI_DEVICE_ID_INTEL_82801DB_0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) case PCI_DEVICE_ID_INTEL_82801E_0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) case PCI_DEVICE_ID_INTEL_82801EB_0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) case PCI_DEVICE_ID_INTEL_ESB_1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) case PCI_DEVICE_ID_INTEL_ICH6_0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) case PCI_DEVICE_ID_INTEL_ICH6_1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) case PCI_DEVICE_ID_INTEL_ICH7_0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) case PCI_DEVICE_ID_INTEL_ICH7_1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) case PCI_DEVICE_ID_INTEL_ICH7_30:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) case PCI_DEVICE_ID_INTEL_ICH7_31:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) case PCI_DEVICE_ID_INTEL_TGP_LPC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) case PCI_DEVICE_ID_INTEL_ESB2_0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) case PCI_DEVICE_ID_INTEL_ICH8_0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) case PCI_DEVICE_ID_INTEL_ICH8_1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) case PCI_DEVICE_ID_INTEL_ICH8_2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) case PCI_DEVICE_ID_INTEL_ICH8_3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) case PCI_DEVICE_ID_INTEL_ICH8_4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) case PCI_DEVICE_ID_INTEL_ICH9_0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) case PCI_DEVICE_ID_INTEL_ICH9_1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) case PCI_DEVICE_ID_INTEL_ICH9_2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) case PCI_DEVICE_ID_INTEL_ICH9_3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) case PCI_DEVICE_ID_INTEL_ICH9_4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) case PCI_DEVICE_ID_INTEL_ICH9_5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) case PCI_DEVICE_ID_INTEL_EP80579_0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) case PCI_DEVICE_ID_INTEL_ICH10_0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) case PCI_DEVICE_ID_INTEL_ICH10_1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) case PCI_DEVICE_ID_INTEL_ICH10_2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) case PCI_DEVICE_ID_INTEL_ICH10_3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) case PCI_DEVICE_ID_INTEL_PATSBURG_LPC_0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) case PCI_DEVICE_ID_INTEL_PATSBURG_LPC_1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) r->name = "PIIX/ICH";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) r->get = pirq_piix_get;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) r->set = pirq_piix_set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) if ((device >= PCI_DEVICE_ID_INTEL_5_3400_SERIES_LPC_MIN &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) device <= PCI_DEVICE_ID_INTEL_5_3400_SERIES_LPC_MAX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) || (device >= PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MIN &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) device <= PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MAX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) || (device >= PCI_DEVICE_ID_INTEL_DH89XXCC_LPC_MIN &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) device <= PCI_DEVICE_ID_INTEL_DH89XXCC_LPC_MAX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) || (device >= PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MIN &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) device <= PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MAX)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) r->name = "PIIX/ICH";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) r->get = pirq_piix_get;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) r->set = pirq_piix_set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) static __init int via_router_probe(struct irq_router *r,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) struct pci_dev *router, u16 device)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) /* FIXME: We should move some of the quirk fixup stuff here */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) * workarounds for some buggy BIOSes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) if (device == PCI_DEVICE_ID_VIA_82C586_0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) switch (router->device) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) case PCI_DEVICE_ID_VIA_82C686:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) * Asus k7m bios wrongly reports 82C686A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) * as 586-compatible
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) device = PCI_DEVICE_ID_VIA_82C686;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) case PCI_DEVICE_ID_VIA_8235:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) * Asus a7v-x bios wrongly reports 8235
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) * as 586-compatible
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) device = PCI_DEVICE_ID_VIA_8235;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) case PCI_DEVICE_ID_VIA_8237:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) * Asus a7v600 bios wrongly reports 8237
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) * as 586-compatible
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) device = PCI_DEVICE_ID_VIA_8237;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) switch (device) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) case PCI_DEVICE_ID_VIA_82C586_0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) r->name = "VIA";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) r->get = pirq_via586_get;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) r->set = pirq_via586_set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) case PCI_DEVICE_ID_VIA_82C596:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) case PCI_DEVICE_ID_VIA_82C686:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) case PCI_DEVICE_ID_VIA_8231:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) case PCI_DEVICE_ID_VIA_8233A:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) case PCI_DEVICE_ID_VIA_8235:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) case PCI_DEVICE_ID_VIA_8237:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) /* FIXME: add new ones for 8233/5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) r->name = "VIA";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) r->get = pirq_via_get;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) r->set = pirq_via_set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) static __init int vlsi_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) switch (device) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) case PCI_DEVICE_ID_VLSI_82C534:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) r->name = "VLSI 82C534";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) r->get = pirq_vlsi_get;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) r->set = pirq_vlsi_set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) static __init int serverworks_router_probe(struct irq_router *r,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) struct pci_dev *router, u16 device)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) switch (device) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) case PCI_DEVICE_ID_SERVERWORKS_OSB4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) case PCI_DEVICE_ID_SERVERWORKS_CSB5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) r->name = "ServerWorks";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) r->get = pirq_serverworks_get;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) r->set = pirq_serverworks_set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) static __init int sis_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) if (device != PCI_DEVICE_ID_SI_503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) r->name = "SIS";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) r->get = pirq_sis_get;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) r->set = pirq_sis_set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) static __init int cyrix_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) switch (device) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) case PCI_DEVICE_ID_CYRIX_5520:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) r->name = "NatSemi";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) r->get = pirq_cyrix_get;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) r->set = pirq_cyrix_set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) static __init int opti_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) switch (device) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) case PCI_DEVICE_ID_OPTI_82C700:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) r->name = "OPTI";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) r->get = pirq_opti_get;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) r->set = pirq_opti_set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) static __init int ite_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) switch (device) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) case PCI_DEVICE_ID_ITE_IT8330G_0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) r->name = "ITE";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) r->get = pirq_ite_get;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) r->set = pirq_ite_set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) static __init int ali_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) switch (device) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) case PCI_DEVICE_ID_AL_M1533:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) case PCI_DEVICE_ID_AL_M1563:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) r->name = "ALI";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) r->get = pirq_ali_get;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) r->set = pirq_ali_set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) static __init int amd_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) switch (device) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) case PCI_DEVICE_ID_AMD_VIPER_740B:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) r->name = "AMD756";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) case PCI_DEVICE_ID_AMD_VIPER_7413:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) r->name = "AMD766";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) case PCI_DEVICE_ID_AMD_VIPER_7443:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) r->name = "AMD768";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) r->get = pirq_amd756_get;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) r->set = pirq_amd756_set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) static __init int pico_router_probe(struct irq_router *r, struct pci_dev *router, u16 device)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) switch (device) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) case PCI_DEVICE_ID_PICOPOWER_PT86C523:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) r->name = "PicoPower PT86C523";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) r->get = pirq_pico_get;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) r->set = pirq_pico_set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) case PCI_DEVICE_ID_PICOPOWER_PT86C523BBP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) r->name = "PicoPower PT86C523 rev. BB+";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) r->get = pirq_pico_get;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) r->set = pirq_pico_set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) static __initdata struct irq_router_handler pirq_routers[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) { PCI_VENDOR_ID_INTEL, intel_router_probe },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) { PCI_VENDOR_ID_AL, ali_router_probe },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) { PCI_VENDOR_ID_ITE, ite_router_probe },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) { PCI_VENDOR_ID_VIA, via_router_probe },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) { PCI_VENDOR_ID_OPTI, opti_router_probe },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) { PCI_VENDOR_ID_SI, sis_router_probe },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) { PCI_VENDOR_ID_CYRIX, cyrix_router_probe },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) { PCI_VENDOR_ID_VLSI, vlsi_router_probe },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) { PCI_VENDOR_ID_SERVERWORKS, serverworks_router_probe },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) { PCI_VENDOR_ID_AMD, amd_router_probe },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) { PCI_VENDOR_ID_PICOPOWER, pico_router_probe },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) /* Someone with docs needs to add the ATI Radeon IGP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) { 0, NULL }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) static struct irq_router pirq_router;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) static struct pci_dev *pirq_router_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) * FIXME: should we have an option to say "generic for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) * chipset" ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) static void __init pirq_find_router(struct irq_router *r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) struct irq_routing_table *rt = pirq_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) struct irq_router_handler *h;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) #ifdef CONFIG_PCI_BIOS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) if (!rt->signature) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) printk(KERN_INFO "PCI: Using BIOS for IRQ routing\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) r->set = pirq_bios_set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) r->name = "BIOS";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) /* Default unless a driver reloads it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) r->name = "default";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) r->get = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) r->set = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) DBG(KERN_DEBUG "PCI: Attempting to find IRQ router for [%04x:%04x]\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) rt->rtr_vendor, rt->rtr_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) pirq_router_dev = pci_get_domain_bus_and_slot(0, rt->rtr_bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) rt->rtr_devfn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) if (!pirq_router_dev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) DBG(KERN_DEBUG "PCI: Interrupt router not found at "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) "%02x:%02x\n", rt->rtr_bus, rt->rtr_devfn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) for (h = pirq_routers; h->vendor; h++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) /* First look for a router match */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) if (rt->rtr_vendor == h->vendor &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) h->probe(r, pirq_router_dev, rt->rtr_device))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) /* Fall back to a device match */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) if (pirq_router_dev->vendor == h->vendor &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) h->probe(r, pirq_router_dev, pirq_router_dev->device))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) dev_info(&pirq_router_dev->dev, "%s IRQ router [%04x:%04x]\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) pirq_router.name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) pirq_router_dev->vendor, pirq_router_dev->device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) /* The device remains referenced for the kernel lifetime */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) static struct irq_info *pirq_get_info(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) struct irq_routing_table *rt = pirq_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) int entries = (rt->size - sizeof(struct irq_routing_table)) /
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) sizeof(struct irq_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) struct irq_info *info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) for (info = rt->slots; entries--; info++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) if (info->bus == dev->bus->number &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) PCI_SLOT(info->devfn) == PCI_SLOT(dev->devfn))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) return info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) static int pcibios_lookup_irq(struct pci_dev *dev, int assign)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) u8 pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) struct irq_info *info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) int i, pirq, newirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) int irq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) u32 mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) struct irq_router *r = &pirq_router;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) struct pci_dev *dev2 = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) char *msg = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) /* Find IRQ pin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) if (!pin) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) dev_dbg(&dev->dev, "no interrupt pin\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) if (io_apic_assign_pci_irqs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) /* Find IRQ routing entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) if (!pirq_table)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) info = pirq_get_info(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) if (!info) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) dev_dbg(&dev->dev, "PCI INT %c not found in routing table\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) 'A' + pin - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) pirq = info->irq[pin - 1].link;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) mask = info->irq[pin - 1].bitmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) if (!pirq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) dev_dbg(&dev->dev, "PCI INT %c not routed\n", 'A' + pin - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) dev_dbg(&dev->dev, "PCI INT %c -> PIRQ %02x, mask %04x, excl %04x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) 'A' + pin - 1, pirq, mask, pirq_table->exclusive_irqs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) mask &= pcibios_irq_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) /* Work around broken HP Pavilion Notebooks which assign USB to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) IRQ 9 even though it is actually wired to IRQ 11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) if (broken_hp_bios_irq9 && pirq == 0x59 && dev->irq == 9) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) dev->irq = 11;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) pci_write_config_byte(dev, PCI_INTERRUPT_LINE, 11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) r->set(pirq_router_dev, dev, pirq, 11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) /* same for Acer Travelmate 360, but with CB and irq 11 -> 10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) if (acer_tm360_irqrouting && dev->irq == 11 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) dev->vendor == PCI_VENDOR_ID_O2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) pirq = 0x68;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) mask = 0x400;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) dev->irq = r->get(pirq_router_dev, dev, pirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) * Find the best IRQ to assign: use the one
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) * reported by the device if possible.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) newirq = dev->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) if (newirq && !((1 << newirq) & mask)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) if (pci_probe & PCI_USE_PIRQ_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) newirq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) dev_warn(&dev->dev, "IRQ %d doesn't match PIRQ mask "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) "%#x; try pci=usepirqmask\n", newirq, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) if (!newirq && assign) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) for (i = 0; i < 16; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) if (!(mask & (1 << i)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) if (pirq_penalty[i] < pirq_penalty[newirq] &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) can_request_irq(i, IRQF_SHARED))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) newirq = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) dev_dbg(&dev->dev, "PCI INT %c -> newirq %d", 'A' + pin - 1, newirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) /* Check if it is hardcoded */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) if ((pirq & 0xf0) == 0xf0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) irq = pirq & 0xf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) msg = "hardcoded";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) } else if (r->get && (irq = r->get(pirq_router_dev, dev, pirq)) && \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) ((!(pci_probe & PCI_USE_PIRQ_MASK)) || ((1 << irq) & mask))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) msg = "found";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) elcr_set_level_irq(irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) } else if (newirq && r->set &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) (dev->class >> 8) != PCI_CLASS_DISPLAY_VGA) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) if (r->set(pirq_router_dev, dev, pirq, newirq)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) elcr_set_level_irq(newirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) msg = "assigned";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) irq = newirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) if (!irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) if (newirq && mask == (1 << newirq)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) msg = "guessed";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) irq = newirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) dev_dbg(&dev->dev, "can't route interrupt\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) dev_info(&dev->dev, "%s PCI INT %c -> IRQ %d\n", msg, 'A' + pin - 1, irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) /* Update IRQ for all devices with the same pirq value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) for_each_pci_dev(dev2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) pci_read_config_byte(dev2, PCI_INTERRUPT_PIN, &pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) if (!pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) info = pirq_get_info(dev2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) if (!info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) if (info->irq[pin - 1].link == pirq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) * We refuse to override the dev->irq
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) * information. Give a warning!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) if (dev2->irq && dev2->irq != irq && \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) (!(pci_probe & PCI_USE_PIRQ_MASK) || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) ((1 << dev2->irq) & mask))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) #ifndef CONFIG_PCI_MSI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) dev_info(&dev2->dev, "IRQ routing conflict: "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) "have IRQ %d, want IRQ %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) dev2->irq, irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) dev2->irq = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) pirq_penalty[irq]++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) if (dev != dev2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) dev_info(&dev->dev, "sharing IRQ %d with %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) irq, pci_name(dev2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) void __init pcibios_fixup_irqs(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) struct pci_dev *dev = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) u8 pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) DBG(KERN_DEBUG "PCI: IRQ fixup\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) for_each_pci_dev(dev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) * If the BIOS has set an out of range IRQ number, just
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) * ignore it. Also keep track of which IRQ's are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) * already in use.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) if (dev->irq >= 16) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) dev_dbg(&dev->dev, "ignoring bogus IRQ %d\n", dev->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) dev->irq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) * If the IRQ is already assigned to a PCI device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) * ignore its ISA use penalty
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) if (pirq_penalty[dev->irq] >= 100 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) pirq_penalty[dev->irq] < 100000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) pirq_penalty[dev->irq] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) pirq_penalty[dev->irq]++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) if (io_apic_assign_pci_irqs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) dev = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) for_each_pci_dev(dev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) if (!pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) * Still no IRQ? Try to lookup one...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) if (!dev->irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) pcibios_lookup_irq(dev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) * Work around broken HP Pavilion Notebooks which assign USB to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) * IRQ 9 even though it is actually wired to IRQ 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) static int __init fix_broken_hp_bios_irq9(const struct dmi_system_id *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) if (!broken_hp_bios_irq9) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) broken_hp_bios_irq9 = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) printk(KERN_INFO "%s detected - fixing broken IRQ routing\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) d->ident);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) * Work around broken Acer TravelMate 360 Notebooks which assign
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) * Cardbus to IRQ 11 even though it is actually wired to IRQ 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) static int __init fix_acer_tm360_irqrouting(const struct dmi_system_id *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) if (!acer_tm360_irqrouting) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) acer_tm360_irqrouting = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) printk(KERN_INFO "%s detected - fixing broken IRQ routing\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) d->ident);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) static const struct dmi_system_id pciirq_dmi_table[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) .callback = fix_broken_hp_bios_irq9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) .ident = "HP Pavilion N5400 Series Laptop",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) .matches = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) DMI_MATCH(DMI_BIOS_VERSION, "GE.M1.03"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) DMI_MATCH(DMI_PRODUCT_VERSION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) "HP Pavilion Notebook Model GE"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) DMI_MATCH(DMI_BOARD_VERSION, "OmniBook N32N-736"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) .callback = fix_acer_tm360_irqrouting,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) .ident = "Acer TravelMate 36x Laptop",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) .matches = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) DMI_MATCH(DMI_PRODUCT_NAME, "TravelMate 360"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) void __init pcibios_irq_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) struct irq_routing_table *rtable = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) DBG(KERN_DEBUG "PCI: IRQ init\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) if (raw_pci_ops == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) dmi_check_system(pciirq_dmi_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) pirq_table = pirq_find_routing_table();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) #ifdef CONFIG_PCI_BIOS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) if (!pirq_table && (pci_probe & PCI_BIOS_IRQ_SCAN)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) pirq_table = pcibios_get_irq_routing_table();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) rtable = pirq_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) if (pirq_table) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) pirq_peer_trick();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) pirq_find_router(&pirq_router);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) if (pirq_table->exclusive_irqs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) for (i = 0; i < 16; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) if (!(pirq_table->exclusive_irqs & (1 << i)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) pirq_penalty[i] += 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) * If we're using the I/O APIC, avoid using the PCI IRQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) * routing table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) if (io_apic_assign_pci_irqs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) kfree(rtable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) pirq_table = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) x86_init.pci.fixup_irqs();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) if (io_apic_assign_pci_irqs && pci_routeirq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) struct pci_dev *dev = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) * PCI IRQ routing is set up by pci_enable_device(), but we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) * also do it here in case there are still broken drivers that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) * don't use pci_enable_device().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) printk(KERN_INFO "PCI: Routing PCI interrupts for all devices because \"pci=routeirq\" specified\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) for_each_pci_dev(dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) pirq_enable_irq(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) static void pirq_penalize_isa_irq(int irq, int active)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) * If any ISAPnP device reports an IRQ in its list of possible
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) * IRQ's, we try to avoid assigning it to PCI devices.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) if (irq < 16) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) if (active)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) pirq_penalty[irq] += 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) pirq_penalty[irq] += 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) void pcibios_penalize_isa_irq(int irq, int active)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) #ifdef CONFIG_ACPI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) if (!acpi_noirq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) acpi_penalize_isa_irq(irq, active);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) pirq_penalize_isa_irq(irq, active);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) static int pirq_enable_irq(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) u8 pin = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) if (pin && !pcibios_lookup_irq(dev, 1)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) char *msg = "";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) if (!io_apic_assign_pci_irqs && dev->irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) if (io_apic_assign_pci_irqs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) #ifdef CONFIG_X86_IO_APIC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) struct pci_dev *temp_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) if (dev->irq_managed && dev->irq > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) irq = IO_APIC_get_PCI_irq_vector(dev->bus->number,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) PCI_SLOT(dev->devfn), pin - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) * Busses behind bridges are typically not listed in the MP-table.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) * In this case we have to look up the IRQ based on the parent bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) * parent slot, and pin number. The SMP code detects such bridged
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) * busses itself so we should get into this branch reliably.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) temp_dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) while (irq < 0 && dev->bus->parent) { /* go back to the bridge */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) struct pci_dev *bridge = dev->bus->self;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) pin = pci_swizzle_interrupt_pin(dev, pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) irq = IO_APIC_get_PCI_irq_vector(bridge->bus->number,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) PCI_SLOT(bridge->devfn),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) pin - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) if (irq >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) dev_warn(&dev->dev, "using bridge %s "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) "INT %c to get IRQ %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) pci_name(bridge), 'A' + pin - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) dev = bridge;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) dev = temp_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) if (irq >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) dev->irq_managed = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) dev->irq = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) dev_info(&dev->dev, "PCI->APIC IRQ transform: "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) "INT %c -> IRQ %d\n", 'A' + pin - 1, irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) msg = "; probably buggy MP table";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) } else if (pci_probe & PCI_BIOS_IRQ_SCAN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) msg = "";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) msg = "; please try using pci=biosirq";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) * With IDE legacy devices the IRQ lookup failure is not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) * a problem..
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) if (dev->class >> 8 == PCI_CLASS_STORAGE_IDE &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) !(dev->class & 0x5))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) dev_warn(&dev->dev, "can't find IRQ for PCI INT %c%s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) 'A' + pin - 1, msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) bool mp_should_keep_irq(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) if (dev->power.is_prepared)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) if (dev->power.runtime_status == RPM_SUSPENDING)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) static void pirq_disable_irq(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) if (io_apic_assign_pci_irqs && !mp_should_keep_irq(&dev->dev) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) dev->irq_managed && dev->irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) mp_unmap_irq(dev->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) dev->irq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) dev->irq_managed = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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