^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Exceptions for specific devices. Usually work-arounds for fatal design flaws.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/dmi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/vgaarb.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <asm/hpet.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <asm/pci_x86.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) static void pci_fixup_i450nx(struct pci_dev *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * i450NX -- Find and scan all secondary buses on all PXB's.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) int pxb, reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) u8 busno, suba, subb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) dev_warn(&d->dev, "Searching for i450NX host bridges\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) reg = 0xd0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) for(pxb = 0; pxb < 2; pxb++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) pci_read_config_byte(d, reg++, &busno);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) pci_read_config_byte(d, reg++, &suba);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) pci_read_config_byte(d, reg++, &subb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) dev_dbg(&d->dev, "i450NX PXB %d: %02x/%02x/%02x\n", pxb, busno,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) suba, subb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) if (busno)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) pcibios_scan_root(busno); /* Bus A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) if (suba < subb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) pcibios_scan_root(suba+1); /* Bus B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) pcibios_last_bus = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82451NX, pci_fixup_i450nx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) static void pci_fixup_i450gx(struct pci_dev *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * i450GX and i450KX -- Find and scan all secondary buses.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * (called separately for each PCI bridge found)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) u8 busno;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) pci_read_config_byte(d, 0x4a, &busno);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) dev_info(&d->dev, "i440KX/GX host bridge; secondary bus %02x\n", busno);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) pcibios_scan_root(busno);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) pcibios_last_bus = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454GX, pci_fixup_i450gx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) static void pci_fixup_umc_ide(struct pci_dev *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * UM8886BF IDE controller sets region type bits incorrectly,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * therefore they look like memory despite of them being I/O.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) dev_warn(&d->dev, "Fixing base address flags\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) for(i = 0; i < 4; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) d->resource[i].flags |= PCI_BASE_ADDRESS_SPACE_IO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_UMC, PCI_DEVICE_ID_UMC_UM8886BF, pci_fixup_umc_ide);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) static void pci_fixup_latency(struct pci_dev *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * SiS 5597 and 5598 chipsets require latency timer set to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) * at most 32 to avoid lockups.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) dev_dbg(&d->dev, "Setting max latency to 32\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) pcibios_max_latency = 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5597, pci_fixup_latency);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5598, pci_fixup_latency);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) static void pci_fixup_piix4_acpi(struct pci_dev *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) * PIIX4 ACPI device: hardwired IRQ9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) d->irq = 9;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, pci_fixup_piix4_acpi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) * Addresses issues with problems in the memory write queue timer in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) * certain VIA Northbridges. This bugfix is per VIA's specifications,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) * except for the KL133/KM133: clearing bit 5 on those Northbridges seems
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) * to trigger a bug in its integrated ProSavage video card, which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) * causes screen corruption. We only clear bits 6 and 7 for that chipset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) * until VIA can provide us with definitive information on why screen
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) * corruption occurs, and what exactly those bits do.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) * VIA 8363,8622,8361 Northbridges:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) * - bits 5, 6, 7 at offset 0x55 need to be turned off
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) * VIA 8367 (KT266x) Northbridges:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) * - bits 5, 6, 7 at offset 0x95 need to be turned off
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) * VIA 8363 rev 0x81/0x84 (KL133/KM133) Northbridges:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) * - bits 6, 7 at offset 0x55 need to be turned off
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define VIA_8363_KL133_REVISION_ID 0x81
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define VIA_8363_KM133_REVISION_ID 0x84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) static void pci_fixup_via_northbridge_bug(struct pci_dev *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) u8 v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) int where = 0x55;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) int mask = 0x1f; /* clear bits 5, 6, 7 by default */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) if (d->device == PCI_DEVICE_ID_VIA_8367_0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) /* fix pci bus latency issues resulted by NB bios error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) it appears on bug free^Wreduced kt266x's bios forces
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) NB latency to zero */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) pci_write_config_byte(d, PCI_LATENCY_TIMER, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) where = 0x95; /* the memory write queue timer register is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) different for the KT266x's: 0x95 not 0x55 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) } else if (d->device == PCI_DEVICE_ID_VIA_8363_0 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) (d->revision == VIA_8363_KL133_REVISION_ID ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) d->revision == VIA_8363_KM133_REVISION_ID)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) mask = 0x3f; /* clear only bits 6 and 7; clearing bit 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) causes screen corruption on the KL133/KM133 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) pci_read_config_byte(d, where, &v);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) if (v & ~mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) dev_warn(&d->dev, "Disabling VIA memory write queue (PCI ID %04x, rev %02x): [%02x] %02x & %02x -> %02x\n", \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) d->device, d->revision, where, v, mask, v & mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) v &= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) pci_write_config_byte(d, where, v);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, pci_fixup_via_northbridge_bug);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8622, pci_fixup_via_northbridge_bug);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, pci_fixup_via_northbridge_bug);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8367_0, pci_fixup_via_northbridge_bug);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, pci_fixup_via_northbridge_bug);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8622, pci_fixup_via_northbridge_bug);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, pci_fixup_via_northbridge_bug);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8367_0, pci_fixup_via_northbridge_bug);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) * For some reasons Intel decided that certain parts of their
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) * 815, 845 and some other chipsets must look like PCI-to-PCI bridges
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) * while they are obviously not. The 82801 family (AA, AB, BAM/CAM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) * BA/CA/DB and E) PCI bridges are actually HUB-to-PCI ones, according
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) * to Intel terminology. These devices do forward all addresses from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) * system to PCI bus no matter what are their window settings, so they are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) * "transparent" (or subtractive decoding) from programmers point of view.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) static void pci_fixup_transparent_bridge(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) if ((dev->device & 0xff00) == 0x2400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) dev->transparent = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_INTEL, PCI_ANY_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) PCI_CLASS_BRIDGE_PCI, 8, pci_fixup_transparent_bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) * Fixup for C1 Halt Disconnect problem on nForce2 systems.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) * From information provided by "Allen Martin" <AMartin@nvidia.com>:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) * A hang is caused when the CPU generates a very fast CONNECT/HALT cycle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) * sequence. Workaround is to set the SYSTEM_IDLE_TIMEOUT to 80 ns.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) * This allows the state-machine and timer to return to a proper state within
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) * 80 ns of the CONNECT and probe appearing together. Since the CPU will not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) * issue another HALT within 80 ns of the initial HALT, the failure condition
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) * is avoided.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) static void pci_fixup_nforce2(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) * Chip Old value New value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) * C17 0x1F0FFF01 0x1F01FF01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) * C18D 0x9F0FFF01 0x9F01FF01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) * Northbridge chip version may be determined by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) * reading the PCI revision ID (0xC1 or greater is C18D).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) pci_read_config_dword(dev, 0x6c, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) * Apply fixup if needed, but don't touch disconnect state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) if ((val & 0x00FF0000) != 0x00010000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) dev_warn(&dev->dev, "nForce2 C1 Halt Disconnect fixup\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) pci_write_config_dword(dev, 0x6c, (val & 0xFF00FFFF) | 0x00010000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2, pci_fixup_nforce2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2, pci_fixup_nforce2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) /* Max PCI Express root ports */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define MAX_PCIEROOT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) static int quirk_aspm_offset[MAX_PCIEROOT << 3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define GET_INDEX(a, b) ((((a) - PCI_DEVICE_ID_INTEL_MCH_PA) << 3) + ((b) & 7))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) static int quirk_pcie_aspm_read(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) return raw_pci_read(pci_domain_nr(bus), bus->number,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) devfn, where, size, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) * Replace the original pci bus ops for write with a new one that will filter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) * the request to insure ASPM cannot be enabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) static int quirk_pcie_aspm_write(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) u8 offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) offset = quirk_aspm_offset[GET_INDEX(bus->self->device, devfn)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) if ((offset) && (where == offset))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) value = value & ~PCI_EXP_LNKCTL_ASPMC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) return raw_pci_write(pci_domain_nr(bus), bus->number,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) devfn, where, size, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) static struct pci_ops quirk_pcie_aspm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) .read = quirk_pcie_aspm_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) .write = quirk_pcie_aspm_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) * Prevents PCI Express ASPM (Active State Power Management) being enabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) * Save the register offset, where the ASPM control bits are located,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) * for each PCI Express device that is in the device list of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) * the root port in an array for fast indexing. Replace the bus ops
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) * with the modified one.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) static void pcie_rootport_aspm_quirk(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) struct pci_bus *pbus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) struct pci_dev *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) if ((pbus = pdev->subordinate) == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) * Check if the DID of pdev matches one of the six root ports. This
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) * check is needed in the case this function is called directly by the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) * hot-plug driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) if ((pdev->device < PCI_DEVICE_ID_INTEL_MCH_PA) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) (pdev->device > PCI_DEVICE_ID_INTEL_MCH_PC1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) if (list_empty(&pbus->devices)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) * If no device is attached to the root port at power-up or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) * after hot-remove, the pbus->devices is empty and this code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) * will set the offsets to zero and the bus ops to parent's bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) * ops, which is unmodified.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) for (i = GET_INDEX(pdev->device, 0); i <= GET_INDEX(pdev->device, 7); ++i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) quirk_aspm_offset[i] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) pci_bus_set_ops(pbus, pbus->parent->ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) * If devices are attached to the root port at power-up or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) * after hot-add, the code loops through the device list of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) * each root port to save the register offsets and replace the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) * bus ops.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) list_for_each_entry(dev, &pbus->devices, bus_list)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) /* There are 0 to 8 devices attached to this bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) quirk_aspm_offset[GET_INDEX(pdev->device, dev->devfn)] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) dev->pcie_cap + PCI_EXP_LNKCTL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) pci_bus_set_ops(pbus, &quirk_pcie_aspm_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) dev_info(&pbus->dev, "writes to ASPM control bits will be ignored\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_MCH_PA, pcie_rootport_aspm_quirk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_MCH_PA1, pcie_rootport_aspm_quirk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_MCH_PB, pcie_rootport_aspm_quirk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_MCH_PB1, pcie_rootport_aspm_quirk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_MCH_PC, pcie_rootport_aspm_quirk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_MCH_PC1, pcie_rootport_aspm_quirk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) * Fixup to mark boot BIOS video selected by BIOS before it changes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) * From information provided by "Jon Smirl" <jonsmirl@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) * The standard boot ROM sequence for an x86 machine uses the BIOS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) * to select an initial video card for boot display. This boot video
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) * card will have its BIOS copied to 0xC0000 in system RAM.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) * IORESOURCE_ROM_SHADOW is used to associate the boot video
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) * card with this copy. On laptops this copy has to be used since
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) * the main ROM may be compressed or combined with another image.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) * See pci_map_rom() for use of this flag. Before marking the device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) * with IORESOURCE_ROM_SHADOW check if a vga_default_device is already set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) * by either arch code or vga-arbitration; if so only apply the fixup to this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) * already-determined primary video card.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) static void pci_fixup_video(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) struct pci_dev *bridge;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) struct pci_bus *bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) u16 config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) /* Is VGA routed to us? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) bus = pdev->bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) while (bus) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) bridge = bus->self;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) * From information provided by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) * "David Miller" <davem@davemloft.net>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) * The bridge control register is valid for PCI header
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) * type BRIDGE, or CARDBUS. Host to PCI controllers use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) * PCI header type NORMAL.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) if (bridge && (pci_is_bridge(bridge))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) pci_read_config_word(bridge, PCI_BRIDGE_CONTROL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) &config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) if (!(config & PCI_BRIDGE_CTL_VGA))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) bus = bus->parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) if (!vga_default_device() || pdev == vga_default_device()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) pci_read_config_word(pdev, PCI_COMMAND, &config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) if (config & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) res = &pdev->resource[PCI_ROM_RESOURCE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) pci_disable_rom(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) if (res->parent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) release_resource(res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) res->start = 0xC0000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) res->end = res->start + 0x20000 - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) res->flags = IORESOURCE_MEM | IORESOURCE_ROM_SHADOW |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) IORESOURCE_PCI_FIXED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) dev_info(&pdev->dev, "Video device with shadowed ROM at %pR\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_ANY_ID, PCI_ANY_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) PCI_CLASS_DISPLAY_VGA, 8, pci_fixup_video);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) static const struct dmi_system_id msi_k8t_dmi_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) .ident = "MSI-K8T-Neo2Fir",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) .matches = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) DMI_MATCH(DMI_SYS_VENDOR, "MSI"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) DMI_MATCH(DMI_PRODUCT_NAME, "MS-6702E"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) * The AMD-Athlon64 board MSI "K8T Neo2-FIR" disables the onboard sound
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) * card if a PCI-soundcard is added.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) * The BIOS only gives options "DISABLED" and "AUTO". This code sets
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) * the corresponding register-value to enable the soundcard.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) * The soundcard is only enabled, if the mainborad is identified
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) * via DMI-tables and the soundcard is detected to be off.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) static void pci_fixup_msi_k8t_onboard_sound(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) unsigned char val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) if (!dmi_check_system(msi_k8t_dmi_table))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) return; /* only applies to MSI K8T Neo2-FIR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) pci_read_config_byte(dev, 0x50, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) if (val & 0x40) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) pci_write_config_byte(dev, 0x50, val & (~0x40));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) /* verify the change for status output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) pci_read_config_byte(dev, 0x50, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) if (val & 0x40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) dev_info(&dev->dev, "Detected MSI K8T Neo2-FIR; "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) "can't enable onboard soundcard!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) dev_info(&dev->dev, "Detected MSI K8T Neo2-FIR; "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) "enabled onboard soundcard\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) pci_fixup_msi_k8t_onboard_sound);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) pci_fixup_msi_k8t_onboard_sound);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) * Some Toshiba laptops need extra code to enable their TI TSB43AB22/A.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) * We pretend to bring them out of full D3 state, and restore the proper
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) * IRQ, PCI cache line size, and BARs, otherwise the device won't function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) * properly. In some cases, the device will generate an interrupt on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) * the wrong IRQ line, causing any devices sharing the line it's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) * *supposed* to use to be disabled by the kernel's IRQ debug code.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) static u16 toshiba_line_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) static const struct dmi_system_id toshiba_ohci1394_dmi_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) .ident = "Toshiba PS5 based laptop",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) .matches = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) DMI_MATCH(DMI_PRODUCT_VERSION, "PS5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) .ident = "Toshiba PSM4 based laptop",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) .matches = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) DMI_MATCH(DMI_PRODUCT_VERSION, "PSM4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) .ident = "Toshiba A40 based laptop",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) .matches = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) DMI_MATCH(DMI_PRODUCT_VERSION, "PSA40U"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) static void pci_pre_fixup_toshiba_ohci1394(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) if (!dmi_check_system(toshiba_ohci1394_dmi_table))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) return; /* only applies to certain Toshibas (so far) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) dev->current_state = PCI_D3cold;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) pci_read_config_word(dev, PCI_CACHE_LINE_SIZE, &toshiba_line_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TI, 0x8032,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) pci_pre_fixup_toshiba_ohci1394);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) static void pci_post_fixup_toshiba_ohci1394(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) if (!dmi_check_system(toshiba_ohci1394_dmi_table))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) return; /* only applies to certain Toshibas (so far) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) /* Restore config space on Toshiba laptops */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) pci_write_config_word(dev, PCI_CACHE_LINE_SIZE, toshiba_line_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) pci_read_config_byte(dev, PCI_INTERRUPT_LINE, (u8 *)&dev->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) pci_write_config_dword(dev, PCI_BASE_ADDRESS_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) pci_resource_start(dev, 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) pci_write_config_dword(dev, PCI_BASE_ADDRESS_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) pci_resource_start(dev, 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_TI, 0x8032,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) pci_post_fixup_toshiba_ohci1394);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) * Prevent the BIOS trapping accesses to the Cyrix CS5530A video device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) * configuration space.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) static void pci_early_fixup_cyrix_5530(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) u8 r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) /* clear 'F4 Video Configuration Trap' bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) pci_read_config_byte(dev, 0x42, &r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) r &= 0xfd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) pci_write_config_byte(dev, 0x42, r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_5530_LEGACY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) pci_early_fixup_cyrix_5530);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_5530_LEGACY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) pci_early_fixup_cyrix_5530);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) * Siemens Nixdorf AG FSC Multiprocessor Interrupt Controller:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) * prevent update of the BAR0, which doesn't look like a normal BAR.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) static void pci_siemens_interrupt_controller(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) dev->resource[0].flags |= IORESOURCE_PCI_FIXED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SIEMENS, 0x0015,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) pci_siemens_interrupt_controller);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) * SB600: Disable BAR1 on device 14.0 to avoid HPET resources from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) * confusing the PCI engine:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) static void sb600_disable_hpet_bar(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) * The SB600 and SB700 both share the same device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) * ID, but the PM register 0x55 does something different
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) * for the SB700, so make sure we are dealing with the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) * SB600 before touching the bit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) pci_read_config_byte(dev, 0x08, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) if (val < 0x2F) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) outb(0x55, 0xCD6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) val = inb(0xCD7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) /* Set bit 7 in PM register 0x55 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) outb(0x55, 0xCD6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) outb(val | 0x80, 0xCD7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_ATI, 0x4385, sb600_disable_hpet_bar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) #ifdef CONFIG_HPET_TIMER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) static void sb600_hpet_quirk(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) struct resource *r = &dev->resource[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) if (r->flags & IORESOURCE_MEM && r->start == hpet_address) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) r->flags |= IORESOURCE_PCI_FIXED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) dev_info(&dev->dev, "reg 0x14 contains HPET; making it immovable\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, 0x4385, sb600_hpet_quirk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) * Twinhead H12Y needs us to block out a region otherwise we map devices
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) * there and any access kills the box.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) * See: https://bugzilla.kernel.org/show_bug.cgi?id=10231
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) * Match off the LPC and svid/sdid (older kernels lose the bridge subvendor)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) static void twinhead_reserve_killing_zone(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) if (dev->subsystem_vendor == 0x14FF && dev->subsystem_device == 0xA003) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) pr_info("Reserving memory on Twinhead H12Y\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) request_mem_region(0xFFB00000, 0x100000, "twinhead");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x27B9, twinhead_reserve_killing_zone);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) * Device [8086:2fc0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) * Erratum HSE43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) * CONFIG_TDP_NOMINAL CSR Implemented at Incorrect Offset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) * https://www.intel.com/content/www/us/en/processors/xeon/xeon-e5-v3-spec-update.html
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) * Devices [8086:6f60,6fa0,6fc0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) * Erratum BDF2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) * PCI BARs in the Home Agent Will Return Non-Zero Values During Enumeration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) * https://www.intel.com/content/www/us/en/processors/xeon/xeon-e5-v4-spec-update.html
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) static void pci_invalid_bar(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) dev->non_compliant_bars = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x2fc0, pci_invalid_bar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x6f60, pci_invalid_bar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x6fa0, pci_invalid_bar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x6fc0, pci_invalid_bar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0xa1ec, pci_invalid_bar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0xa1ed, pci_invalid_bar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0xa26c, pci_invalid_bar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0xa26d, pci_invalid_bar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) * Device [1022:7808]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) * 23. USB Wake on Connect/Disconnect with Low Speed Devices
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) * https://support.amd.com/TechDocs/46837.pdf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) * Appendix A2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) * https://support.amd.com/TechDocs/42413.pdf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) static void pci_fixup_amd_ehci_pme(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) dev_info(&dev->dev, "PME# does not work under D3, disabling it\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) dev->pme_support &= ~((PCI_PM_CAP_PME_D3hot | PCI_PM_CAP_PME_D3cold)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) >> PCI_PM_CAP_PME_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x7808, pci_fixup_amd_ehci_pme);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) * Device [1022:7914]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) * When in D0, PME# doesn't get asserted when plugging USB 2.0 device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) static void pci_fixup_amd_fch_xhci_pme(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) dev_info(&dev->dev, "PME# does not work under D0, disabling it\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) dev->pme_support &= ~(PCI_PM_CAP_PME_D0 >> PCI_PM_CAP_PME_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x7914, pci_fixup_amd_fch_xhci_pme);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) * Apple MacBook Pro: Avoid [mem 0x7fa00000-0x7fbfffff]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) * Using the [mem 0x7fa00000-0x7fbfffff] region, e.g., by assigning it to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) * the 00:1c.0 Root Port, causes a conflict with [io 0x1804], which is used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) * for soft poweroff and suspend-to-RAM.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) * As far as we know, this is related to the address space, not to the Root
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) * Port itself. Attaching the quirk to the Root Port is a convenience, but
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) * it could probably also be a standalone DMI quirk.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) * https://bugzilla.kernel.org/show_bug.cgi?id=103211
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) static void quirk_apple_mbp_poweroff(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) if ((!dmi_match(DMI_PRODUCT_NAME, "MacBookPro11,4") &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) !dmi_match(DMI_PRODUCT_NAME, "MacBookPro11,5")) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x1c, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) res = request_mem_region(0x7fa00000, 0x200000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) "MacBook Pro poweroff workaround");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) if (res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) dev_info(dev, "claimed %s %pR\n", res->name, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) dev_info(dev, "can't work around MacBook Pro poweroff issue\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x8c10, quirk_apple_mbp_poweroff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) * VMD-enabled root ports will change the source ID for all messages
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) * to the VMD device. Rather than doing device matching with the source
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) * ID, the AER driver should traverse the child device tree, reading
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) * AER registers to find the faulting device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) static void quirk_no_aersid(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) /* VMD Domain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) if (is_vmd(pdev->bus) && pci_is_root_bus(pdev->bus))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) pdev->bus->bus_flags |= PCI_BUS_FLAGS_NO_AERSID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, PCI_ANY_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) PCI_CLASS_BRIDGE_PCI, 8, quirk_no_aersid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) static void quirk_intel_th_dnv(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) struct resource *r = &dev->resource[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) * Denverton reports 2k of RTIT_BAR (intel_th resource 4), which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) * appears to be 4 MB in reality.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) if (r->end == r->start + 0x7ff) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) r->start = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) r->end = 0x3fffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) r->flags |= IORESOURCE_UNSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x19e1, quirk_intel_th_dnv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) #ifdef CONFIG_PHYS_ADDR_T_64BIT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) #define AMD_141b_MMIO_BASE(x) (0x80 + (x) * 0x8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) #define AMD_141b_MMIO_BASE_RE_MASK BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) #define AMD_141b_MMIO_BASE_WE_MASK BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) #define AMD_141b_MMIO_BASE_MMIOBASE_MASK GENMASK(31,8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) #define AMD_141b_MMIO_LIMIT(x) (0x84 + (x) * 0x8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) #define AMD_141b_MMIO_LIMIT_MMIOLIMIT_MASK GENMASK(31,8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) #define AMD_141b_MMIO_HIGH(x) (0x180 + (x) * 0x4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) #define AMD_141b_MMIO_HIGH_MMIOBASE_MASK GENMASK(7,0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) #define AMD_141b_MMIO_HIGH_MMIOLIMIT_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) #define AMD_141b_MMIO_HIGH_MMIOLIMIT_MASK GENMASK(23,16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) * The PCI Firmware Spec, rev 3.2, notes that ACPI should optionally allow
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) * configuring host bridge windows using the _PRS and _SRS methods.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) * But this is rarely implemented, so we manually enable a large 64bit BAR for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) * PCIe device on AMD Family 15h (Models 00h-1fh, 30h-3fh, 60h-7fh) Processors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) * here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) static void pci_amd_enable_64bit_bar(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) static const char *name = "PCI Bus 0000:00";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) struct resource *res, *conflict;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) u32 base, limit, high;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) struct pci_dev *other;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) unsigned i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) if (!(pci_probe & PCI_BIG_ROOT_WINDOW))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) /* Check that we are the only device of that type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) other = pci_get_device(dev->vendor, dev->device, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) if (other != dev ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) (other = pci_get_device(dev->vendor, dev->device, other))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) /* This is a multi-socket system, don't touch it for now */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) pci_dev_put(other);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) for (i = 0; i < 8; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) pci_read_config_dword(dev, AMD_141b_MMIO_BASE(i), &base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) pci_read_config_dword(dev, AMD_141b_MMIO_HIGH(i), &high);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) /* Is this slot free? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) if (!(base & (AMD_141b_MMIO_BASE_RE_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) AMD_141b_MMIO_BASE_WE_MASK)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) base >>= 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) base |= high << 24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) /* Abort if a slot already configures a 64bit BAR. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) if (base > 0x10000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) if (i == 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) res = kzalloc(sizeof(*res), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) if (!res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) * Allocate a 256GB window directly below the 0xfd00000000 hardware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) * limit (see AMD Family 15h Models 30h-3Fh BKDG, sec 2.4.6).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) res->name = name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) res->flags = IORESOURCE_PREFETCH | IORESOURCE_MEM |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) IORESOURCE_MEM_64 | IORESOURCE_WINDOW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) res->start = 0xbd00000000ull;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) res->end = 0xfd00000000ull - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) conflict = request_resource_conflict(&iomem_resource, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) if (conflict) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) kfree(res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) if (conflict->name != name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) /* We are resuming from suspend; just reenable the window */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) res = conflict;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) dev_info(&dev->dev, "adding root bus resource %pR (tainting kernel)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) add_taint(TAINT_FIRMWARE_WORKAROUND, LOCKDEP_STILL_OK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) pci_bus_add_resource(dev->bus, res, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) base = ((res->start >> 8) & AMD_141b_MMIO_BASE_MMIOBASE_MASK) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) AMD_141b_MMIO_BASE_RE_MASK | AMD_141b_MMIO_BASE_WE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) limit = ((res->end + 1) >> 8) & AMD_141b_MMIO_LIMIT_MMIOLIMIT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) high = ((res->start >> 40) & AMD_141b_MMIO_HIGH_MMIOBASE_MASK) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) ((((res->end + 1) >> 40) << AMD_141b_MMIO_HIGH_MMIOLIMIT_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) & AMD_141b_MMIO_HIGH_MMIOLIMIT_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) pci_write_config_dword(dev, AMD_141b_MMIO_HIGH(i), high);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) pci_write_config_dword(dev, AMD_141b_MMIO_LIMIT(i), limit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) pci_write_config_dword(dev, AMD_141b_MMIO_BASE(i), base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x1401, pci_amd_enable_64bit_bar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x141b, pci_amd_enable_64bit_bar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x1571, pci_amd_enable_64bit_bar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x15b1, pci_amd_enable_64bit_bar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x1601, pci_amd_enable_64bit_bar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, 0x1401, pci_amd_enable_64bit_bar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, 0x141b, pci_amd_enable_64bit_bar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, 0x1571, pci_amd_enable_64bit_bar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, 0x15b1, pci_amd_enable_64bit_bar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, 0x1601, pci_amd_enable_64bit_bar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) #define RS690_LOWER_TOP_OF_DRAM2 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) #define RS690_LOWER_TOP_OF_DRAM2_VALID 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) #define RS690_UPPER_TOP_OF_DRAM2 0x31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) #define RS690_HTIU_NB_INDEX 0xA8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) #define RS690_HTIU_NB_INDEX_WR_ENABLE 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) #define RS690_HTIU_NB_DATA 0xAC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) * Some BIOS implementations support RAM above 4GB, but do not configure the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) * PCI host to respond to bus master accesses for these addresses. These
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) * implementations set the TOP_OF_DRAM_SLOT1 register correctly, so PCI DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) * works as expected for addresses below 4GB.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) * Reference: "AMD RS690 ASIC Family Register Reference Guide" (pg. 2-57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) * https://www.amd.com/system/files/TechDocs/43372_rs690_rrg_3.00o.pdf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) static void rs690_fix_64bit_dma(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) u32 val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) phys_addr_t top_of_dram = __pa(high_memory - 1) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) if (top_of_dram <= (1ULL << 32))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) pci_write_config_dword(pdev, RS690_HTIU_NB_INDEX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) RS690_LOWER_TOP_OF_DRAM2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) pci_read_config_dword(pdev, RS690_HTIU_NB_DATA, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) if (val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) pci_info(pdev, "Adjusting top of DRAM to %pa for 64-bit DMA support\n", &top_of_dram);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) pci_write_config_dword(pdev, RS690_HTIU_NB_INDEX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) RS690_UPPER_TOP_OF_DRAM2 | RS690_HTIU_NB_INDEX_WR_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) pci_write_config_dword(pdev, RS690_HTIU_NB_DATA, top_of_dram >> 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) pci_write_config_dword(pdev, RS690_HTIU_NB_INDEX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) RS690_LOWER_TOP_OF_DRAM2 | RS690_HTIU_NB_INDEX_WR_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) pci_write_config_dword(pdev, RS690_HTIU_NB_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) top_of_dram | RS690_LOWER_TOP_OF_DRAM2_VALID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7910, rs690_fix_64bit_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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