Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) #include <asm/pci-direct.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) #include <asm/pci_x86.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) /* Direct PCI access. This is used for PCI accesses in early boot before
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9)    the PCI subsystem works. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) u32 read_pci_config(u8 bus, u8 slot, u8 func, u8 offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 	u32 v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 	outl(0x80000000 | (bus<<16) | (slot<<11) | (func<<8) | offset, 0xcf8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 	v = inl(0xcfc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 	return v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) u8 read_pci_config_byte(u8 bus, u8 slot, u8 func, u8 offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 	u8 v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 	outl(0x80000000 | (bus<<16) | (slot<<11) | (func<<8) | offset, 0xcf8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 	v = inb(0xcfc + (offset&3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 	return v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) u16 read_pci_config_16(u8 bus, u8 slot, u8 func, u8 offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 	u16 v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 	outl(0x80000000 | (bus<<16) | (slot<<11) | (func<<8) | offset, 0xcf8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 	v = inw(0xcfc + (offset&2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 	return v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) void write_pci_config(u8 bus, u8 slot, u8 func, u8 offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 				    u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 	outl(0x80000000 | (bus<<16) | (slot<<11) | (func<<8) | offset, 0xcf8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 	outl(val, 0xcfc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) void write_pci_config_byte(u8 bus, u8 slot, u8 func, u8 offset, u8 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 	outl(0x80000000 | (bus<<16) | (slot<<11) | (func<<8) | offset, 0xcf8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 	outb(val, 0xcfc + (offset&3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) void write_pci_config_16(u8 bus, u8 slot, u8 func, u8 offset, u16 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 	outl(0x80000000 | (bus<<16) | (slot<<11) | (func<<8) | offset, 0xcf8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 	outw(val, 0xcfc + (offset&2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) int early_pci_allowed(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 	return (pci_probe & (PCI_PROBE_CONF1|PCI_PROBE_NOEARLY)) ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 			PCI_PROBE_CONF1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)