Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * direct.c - Low-level direct PCI config space access
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/dmi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <asm/pci_x86.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  * Functions for accessing PCI base (first 256 bytes) and extended
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13)  * (4096 bytes per PCI function) configuration space with type 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14)  * accesses.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #define PCI_CONF1_ADDRESS(bus, devfn, reg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 	(0x80000000 | ((reg & 0xF00) << 16) | (bus << 16) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 	| (devfn << 8) | (reg & 0xFC))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) static int pci_conf1_read(unsigned int seg, unsigned int bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 			  unsigned int devfn, int reg, int len, u32 *value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 	if (seg || (bus > 255) || (devfn > 255) || (reg > 4095)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 		*value = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	raw_spin_lock_irqsave(&pci_config_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	outl(PCI_CONF1_ADDRESS(bus, devfn, reg), 0xCF8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	switch (len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 		*value = inb(0xCFC + (reg & 3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 		*value = inw(0xCFC + (reg & 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 		*value = inl(0xCFC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	raw_spin_unlock_irqrestore(&pci_config_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) static int pci_conf1_write(unsigned int seg, unsigned int bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 			   unsigned int devfn, int reg, int len, u32 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	if (seg || (bus > 255) || (devfn > 255) || (reg > 4095))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	raw_spin_lock_irqsave(&pci_config_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	outl(PCI_CONF1_ADDRESS(bus, devfn, reg), 0xCF8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	switch (len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 		outb((u8)value, 0xCFC + (reg & 3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 		outw((u16)value, 0xCFC + (reg & 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 		outl((u32)value, 0xCFC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	raw_spin_unlock_irqrestore(&pci_config_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #undef PCI_CONF1_ADDRESS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) const struct pci_raw_ops pci_direct_conf1 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	.read =		pci_conf1_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	.write =	pci_conf1_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90)  * Functions for accessing PCI configuration space with type 2 accesses
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) #define PCI_CONF2_ADDRESS(dev, reg)	(u16)(0xC000 | (dev << 8) | reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) static int pci_conf2_read(unsigned int seg, unsigned int bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 			  unsigned int devfn, int reg, int len, u32 *value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	int dev, fn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	WARN_ON(seg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	if ((bus > 255) || (devfn > 255) || (reg > 255)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 		*value = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	dev = PCI_SLOT(devfn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	fn = PCI_FUNC(devfn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	if (dev & 0x10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 		return PCIBIOS_DEVICE_NOT_FOUND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	raw_spin_lock_irqsave(&pci_config_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	outb((u8)(0xF0 | (fn << 1)), 0xCF8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	outb((u8)bus, 0xCFA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	switch (len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 		*value = inb(PCI_CONF2_ADDRESS(dev, reg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 		*value = inw(PCI_CONF2_ADDRESS(dev, reg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 		*value = inl(PCI_CONF2_ADDRESS(dev, reg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	outb(0, 0xCF8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	raw_spin_unlock_irqrestore(&pci_config_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) static int pci_conf2_write(unsigned int seg, unsigned int bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 			   unsigned int devfn, int reg, int len, u32 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	int dev, fn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	WARN_ON(seg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	if ((bus > 255) || (devfn > 255) || (reg > 255)) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	dev = PCI_SLOT(devfn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	fn = PCI_FUNC(devfn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	if (dev & 0x10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 		return PCIBIOS_DEVICE_NOT_FOUND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	raw_spin_lock_irqsave(&pci_config_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	outb((u8)(0xF0 | (fn << 1)), 0xCF8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	outb((u8)bus, 0xCFA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	switch (len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 		outb((u8)value, PCI_CONF2_ADDRESS(dev, reg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 		outw((u16)value, PCI_CONF2_ADDRESS(dev, reg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 		outl((u32)value, PCI_CONF2_ADDRESS(dev, reg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	outb(0, 0xCF8);    
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	raw_spin_unlock_irqrestore(&pci_config_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #undef PCI_CONF2_ADDRESS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) static const struct pci_raw_ops pci_direct_conf2 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	.read =		pci_conf2_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	.write =	pci_conf2_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)  * Before we decide to use direct hardware access mechanisms, we try to do some
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)  * trivial checks to ensure it at least _seems_ to be working -- we just test
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)  * whether bus 00 contains a host bridge (this is similar to checking
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)  * techniques used in XFree86, but ours should be more reliable since we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)  * attempt to make use of direct access hints provided by the PCI BIOS).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)  * This should be close to trivial, but it isn't, because there are buggy
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)  * chipsets (yes, you guessed it, by Intel and Compaq) that have no class ID.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) static int __init pci_sanity_check(const struct pci_raw_ops *o)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	u32 x = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	int devfn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	if (pci_probe & PCI_NO_CHECKS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 		return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	/* Assume Type 1 works for newer systems.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	   This handles machines that don't have anything on PCI Bus 0. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	if (dmi_get_bios_year() >= 2001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 		return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	for (devfn = 0; devfn < 0x100; devfn++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 		if (o->read(0, 0, devfn, PCI_CLASS_DEVICE, 2, &x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 			continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 		if (x == PCI_CLASS_BRIDGE_HOST || x == PCI_CLASS_DISPLAY_VGA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 			return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 		if (o->read(0, 0, devfn, PCI_VENDOR_ID, 2, &x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 			continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 		if (x == PCI_VENDOR_ID_INTEL || x == PCI_VENDOR_ID_COMPAQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 			return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	DBG(KERN_WARNING "PCI: Sanity check failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) static int __init pci_check_type1(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	unsigned int tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	int works = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	local_irq_save(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	outb(0x01, 0xCFB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	tmp = inl(0xCF8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	outl(0x80000000, 0xCF8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	if (inl(0xCF8) == 0x80000000 && pci_sanity_check(&pci_direct_conf1)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 		works = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	outl(tmp, 0xCF8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	local_irq_restore(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	return works;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) static int __init pci_check_type2(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	int works = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	local_irq_save(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	outb(0x00, 0xCFB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	outb(0x00, 0xCF8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	outb(0x00, 0xCFA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	if (inb(0xCF8) == 0x00 && inb(0xCFA) == 0x00 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	    pci_sanity_check(&pci_direct_conf2)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 		works = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	local_irq_restore(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	return works;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) void __init pci_direct_init(int type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	if (type == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	printk(KERN_INFO "PCI: Using configuration type %d for base access\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 		 type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	if (type == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 		raw_pci_ops = &pci_direct_conf1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 		if (raw_pci_ext_ops)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 			return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 		if (!(pci_probe & PCI_HAS_IO_ECS))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 			return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 		printk(KERN_INFO "PCI: Using configuration type 1 "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 		       "for extended access\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 		raw_pci_ext_ops = &pci_direct_conf1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	raw_pci_ops = &pci_direct_conf2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) int __init pci_direct_probe(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	if ((pci_probe & PCI_PROBE_CONF1) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 		goto type2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	if (!request_region(0xCF8, 8, "PCI conf1"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 		goto type2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	if (pci_check_type1()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 		raw_pci_ops = &pci_direct_conf1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 		port_cf9_safe = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 		return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	release_region(0xCF8, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)  type2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	if ((pci_probe & PCI_PROBE_CONF2) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	if (!request_region(0xCF8, 4, "PCI conf2"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	if (!request_region(0xC000, 0x1000, "PCI conf2"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 		goto fail2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	if (pci_check_type2()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 		raw_pci_ops = &pci_direct_conf2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 		port_cf9_safe = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 		return 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	release_region(0xC000, 0x1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)  fail2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	release_region(0xCF8, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) }