^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright(c) 2010 Intel Corporation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Contact Information:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Intel Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * 2200 Mission College Blvd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Santa Clara, CA 97052
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * This provides access methods for PCI registers that mis-behave on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * the CE4100. Each register can be assigned a private init, read and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * write routine. The exception to this is the bridge device. The
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * bridge device is the only device on bus zero (0) that requires any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * fixup so it is a special case ATM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <asm/ce4100.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <asm/pci_x86.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) struct sim_reg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) u32 mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) struct sim_dev_reg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) int dev_func;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) int reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) void (*init)(struct sim_dev_reg *reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) void (*read)(struct sim_dev_reg *reg, u32 *value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) void (*write)(struct sim_dev_reg *reg, u32 value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) struct sim_reg sim_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) struct sim_reg_op {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) void (*init)(struct sim_dev_reg *reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) void (*read)(struct sim_dev_reg *reg, u32 value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) void (*write)(struct sim_dev_reg *reg, u32 value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define MB (1024 * 1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define KB (1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define SIZE_TO_MASK(size) (~(size - 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define DEFINE_REG(device, func, offset, size, init_op, read_op, write_op)\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) { PCI_DEVFN(device, func), offset, init_op, read_op, write_op,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) {0, SIZE_TO_MASK(size)} },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * All read/write functions are called with pci_config_lock held.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) static void reg_init(struct sim_dev_reg *reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) pci_direct_conf1.read(0, 1, reg->dev_func, reg->reg, 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) ®->sim_reg.value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) static void reg_read(struct sim_dev_reg *reg, u32 *value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) *value = reg->sim_reg.value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) static void reg_write(struct sim_dev_reg *reg, u32 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) reg->sim_reg.value = (value & reg->sim_reg.mask) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) (reg->sim_reg.value & ~reg->sim_reg.mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) static void sata_reg_init(struct sim_dev_reg *reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) pci_direct_conf1.read(0, 1, PCI_DEVFN(14, 0), 0x10, 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) ®->sim_reg.value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) reg->sim_reg.value += 0x400;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) static void ehci_reg_read(struct sim_dev_reg *reg, u32 *value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) reg_read(reg, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) if (*value != reg->sim_reg.mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) *value |= 0x100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) void sata_revid_init(struct sim_dev_reg *reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) reg->sim_reg.value = 0x01060100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) reg->sim_reg.mask = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) static void sata_revid_read(struct sim_dev_reg *reg, u32 *value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) reg_read(reg, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) static void reg_noirq_read(struct sim_dev_reg *reg, u32 *value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) /* force interrupt pin value to 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) *value = reg->sim_reg.value & 0xfff00ff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) static struct sim_dev_reg bus1_fixups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) DEFINE_REG(2, 0, 0x10, (16*MB), reg_init, reg_read, reg_write)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) DEFINE_REG(2, 0, 0x14, (256), reg_init, reg_read, reg_write)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) DEFINE_REG(2, 1, 0x10, (64*KB), reg_init, reg_read, reg_write)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) DEFINE_REG(3, 0, 0x10, (64*KB), reg_init, reg_read, reg_write)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) DEFINE_REG(4, 0, 0x10, (128*KB), reg_init, reg_read, reg_write)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) DEFINE_REG(4, 1, 0x10, (128*KB), reg_init, reg_read, reg_write)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) DEFINE_REG(6, 0, 0x10, (512*KB), reg_init, reg_read, reg_write)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) DEFINE_REG(6, 1, 0x10, (512*KB), reg_init, reg_read, reg_write)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) DEFINE_REG(6, 2, 0x10, (64*KB), reg_init, reg_read, reg_write)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) DEFINE_REG(8, 0, 0x10, (1*MB), reg_init, reg_read, reg_write)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) DEFINE_REG(8, 1, 0x10, (64*KB), reg_init, reg_read, reg_write)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) DEFINE_REG(8, 2, 0x10, (64*KB), reg_init, reg_read, reg_write)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) DEFINE_REG(9, 0, 0x10 , (1*MB), reg_init, reg_read, reg_write)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) DEFINE_REG(9, 0, 0x14, (64*KB), reg_init, reg_read, reg_write)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) DEFINE_REG(10, 0, 0x10, (256), reg_init, reg_read, reg_write)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) DEFINE_REG(10, 0, 0x14, (256*MB), reg_init, reg_read, reg_write)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) DEFINE_REG(11, 0, 0x10, (256), reg_init, reg_read, reg_write)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) DEFINE_REG(11, 0, 0x14, (256), reg_init, reg_read, reg_write)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) DEFINE_REG(11, 1, 0x10, (256), reg_init, reg_read, reg_write)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) DEFINE_REG(11, 2, 0x10, (256), reg_init, reg_read, reg_write)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) DEFINE_REG(11, 2, 0x14, (256), reg_init, reg_read, reg_write)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) DEFINE_REG(11, 2, 0x18, (256), reg_init, reg_read, reg_write)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) DEFINE_REG(11, 3, 0x10, (256), reg_init, reg_read, reg_write)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) DEFINE_REG(11, 3, 0x14, (256), reg_init, reg_read, reg_write)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) DEFINE_REG(11, 4, 0x10, (256), reg_init, reg_read, reg_write)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) DEFINE_REG(11, 5, 0x10, (64*KB), reg_init, reg_read, reg_write)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) DEFINE_REG(11, 6, 0x10, (256), reg_init, reg_read, reg_write)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) DEFINE_REG(11, 7, 0x10, (64*KB), reg_init, reg_read, reg_write)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) DEFINE_REG(11, 7, 0x3c, 256, reg_init, reg_noirq_read, reg_write)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) DEFINE_REG(12, 0, 0x10, (128*KB), reg_init, reg_read, reg_write)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) DEFINE_REG(12, 0, 0x14, (256), reg_init, reg_read, reg_write)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) DEFINE_REG(12, 1, 0x10, (1024), reg_init, reg_read, reg_write)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) DEFINE_REG(13, 0, 0x10, (32*KB), reg_init, ehci_reg_read, reg_write)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) DEFINE_REG(13, 1, 0x10, (32*KB), reg_init, ehci_reg_read, reg_write)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) DEFINE_REG(14, 0, 0x8, 0, sata_revid_init, sata_revid_read, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) DEFINE_REG(14, 0, 0x10, 0, reg_init, reg_read, reg_write)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) DEFINE_REG(14, 0, 0x14, 0, reg_init, reg_read, reg_write)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) DEFINE_REG(14, 0, 0x18, 0, reg_init, reg_read, reg_write)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) DEFINE_REG(14, 0, 0x1C, 0, reg_init, reg_read, reg_write)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) DEFINE_REG(14, 0, 0x20, 0, reg_init, reg_read, reg_write)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) DEFINE_REG(14, 0, 0x24, (0x200), sata_reg_init, reg_read, reg_write)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) DEFINE_REG(15, 0, 0x10, (64*KB), reg_init, reg_read, reg_write)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) DEFINE_REG(15, 0, 0x14, (64*KB), reg_init, reg_read, reg_write)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) DEFINE_REG(16, 0, 0x10, (64*KB), reg_init, reg_read, reg_write)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) DEFINE_REG(16, 0, 0x14, (64*MB), reg_init, reg_read, reg_write)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) DEFINE_REG(16, 0, 0x18, (64*MB), reg_init, reg_read, reg_write)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) DEFINE_REG(16, 0, 0x3c, 256, reg_init, reg_noirq_read, reg_write)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) DEFINE_REG(17, 0, 0x10, (128*KB), reg_init, reg_read, reg_write)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) DEFINE_REG(18, 0, 0x10, (1*KB), reg_init, reg_read, reg_write)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) DEFINE_REG(18, 0, 0x3c, 256, reg_init, reg_noirq_read, reg_write)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) static void __init init_sim_regs(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) for (i = 0; i < ARRAY_SIZE(bus1_fixups); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) if (bus1_fixups[i].init)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) bus1_fixups[i].init(&bus1_fixups[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) static inline void extract_bytes(u32 *value, int reg, int len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) uint32_t mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) *value >>= ((reg & 3) * 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) mask = 0xFFFFFFFF >> ((4 - len) * 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) *value &= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) int bridge_read(unsigned int devfn, int reg, int len, u32 *value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) u32 av_bridge_base, av_bridge_limit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) int retval = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) switch (reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) /* Make BARs appear to not request any memory. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) case PCI_BASE_ADDRESS_0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) case PCI_BASE_ADDRESS_0 + 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) case PCI_BASE_ADDRESS_0 + 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) case PCI_BASE_ADDRESS_0 + 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) *value = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) /* Since subordinate bus number register is hardwired
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) * to zero and read only, so do the simulation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) case PCI_PRIMARY_BUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) if (len == 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) *value = 0x00010100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) case PCI_SUBORDINATE_BUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) *value = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) case PCI_MEMORY_BASE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) case PCI_MEMORY_LIMIT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) /* Get the A/V bridge base address. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) pci_direct_conf1.read(0, 0, devfn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) PCI_BASE_ADDRESS_0, 4, &av_bridge_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) av_bridge_limit = av_bridge_base + (512*MB - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) av_bridge_limit >>= 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) av_bridge_limit &= 0xFFF0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) av_bridge_base >>= 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) av_bridge_base &= 0xFFF0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) if (reg == PCI_MEMORY_LIMIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) *value = av_bridge_limit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) else if (len == 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) *value = av_bridge_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) *value = (av_bridge_limit << 16) | av_bridge_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) /* Make prefetchable memory limit smaller than prefetchable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) * memory base, so not claim prefetchable memory space.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) case PCI_PREF_MEMORY_BASE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) *value = 0xFFF0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) case PCI_PREF_MEMORY_LIMIT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) *value = 0x0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) /* Make IO limit smaller than IO base, so not claim IO space. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) case PCI_IO_BASE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) *value = 0xF0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) case PCI_IO_LIMIT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) *value = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) retval = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) static int ce4100_bus1_read(unsigned int devfn, int reg, int len, u32 *value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) for (i = 0; i < ARRAY_SIZE(bus1_fixups); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) if (bus1_fixups[i].dev_func == devfn &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) bus1_fixups[i].reg == (reg & ~3) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) bus1_fixups[i].read) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) raw_spin_lock_irqsave(&pci_config_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) bus1_fixups[i].read(&(bus1_fixups[i]), value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) raw_spin_unlock_irqrestore(&pci_config_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) extract_bytes(value, reg, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) static int ce4100_conf_read(unsigned int seg, unsigned int bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) unsigned int devfn, int reg, int len, u32 *value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) WARN_ON(seg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) if (bus == 1 && !ce4100_bus1_read(devfn, reg, len, value))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) if (bus == 0 && (PCI_DEVFN(1, 0) == devfn) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) !bridge_read(devfn, reg, len, value))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) return pci_direct_conf1.read(seg, bus, devfn, reg, len, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) static int ce4100_bus1_write(unsigned int devfn, int reg, int len, u32 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) for (i = 0; i < ARRAY_SIZE(bus1_fixups); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) if (bus1_fixups[i].dev_func == devfn &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) bus1_fixups[i].reg == (reg & ~3) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) bus1_fixups[i].write) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) raw_spin_lock_irqsave(&pci_config_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) bus1_fixups[i].write(&(bus1_fixups[i]), value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) raw_spin_unlock_irqrestore(&pci_config_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) static int ce4100_conf_write(unsigned int seg, unsigned int bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) unsigned int devfn, int reg, int len, u32 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) WARN_ON(seg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) if (bus == 1 && !ce4100_bus1_write(devfn, reg, len, value))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) /* Discard writes to A/V bridge BAR. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) if (bus == 0 && PCI_DEVFN(1, 0) == devfn &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) ((reg & ~3) == PCI_BASE_ADDRESS_0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) return pci_direct_conf1.write(seg, bus, devfn, reg, len, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) static const struct pci_raw_ops ce4100_pci_conf = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) .read = ce4100_conf_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) .write = ce4100_conf_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) int __init ce4100_pci_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) init_sim_regs();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) raw_pci_ops = &ce4100_pci_conf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) /* Indicate caller that it should invoke pci_legacy_init() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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