Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*---------------------------------------------------------------------------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  |  control_w.h                                                              |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  |                                                                           |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  | Copyright (C) 1992,1993                                                   |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  |                       W. Metzenthen, 22 Parker St, Ormond, Vic 3163,      |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  |                       Australia.  E-mail   billm@vaxc.cc.monash.edu.au    |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)  |                                                                           |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9)  +---------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #ifndef _CONTROLW_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define _CONTROLW_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #ifdef __ASSEMBLY__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define	_Const_(x)	$##x
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define	_Const_(x)	x
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define CW_RC		_Const_(0x0C00)	/* rounding control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define CW_PC		_Const_(0x0300)	/* precision control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define CW_Precision	Const_(0x0020)	/* loss of precision mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define CW_Underflow	Const_(0x0010)	/* underflow mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define CW_Overflow	Const_(0x0008)	/* overflow mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define CW_ZeroDiv	Const_(0x0004)	/* divide by zero mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define CW_Denormal	Const_(0x0002)	/* denormalized operand mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define CW_Invalid	Const_(0x0001)	/* invalid operation mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define CW_Exceptions  	_Const_(0x003f)	/* all masks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define RC_RND		_Const_(0x0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define RC_DOWN		_Const_(0x0400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define RC_UP		_Const_(0x0800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define RC_CHOP		_Const_(0x0C00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) /* p 15-5: Precision control bits affect only the following:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)    ADD, SUB(R), MUL, DIV(R), and SQRT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define PR_24_BITS        _Const_(0x000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define PR_53_BITS        _Const_(0x200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define PR_64_BITS        _Const_(0x300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define PR_RESERVED_BITS  _Const_(0x100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) /* FULL_PRECISION simulates all exceptions masked */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define FULL_PRECISION  (PR_64_BITS | RC_RND | 0x3f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #endif /* _CONTROLW_H_ */