^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Precise Delay Loops for i386
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 1993 Linus Torvalds
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 1997 Martin Mares <mj@atrey.karlin.mff.cuni.cz>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) 2008 Jiri Hladky <hladky _dot_ jiri _at_ gmail _dot_ com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * The __delay function must _NOT_ be inlined as its execution time
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * depends wildly on alignment on many x86 processors. The additional
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * jump magic is needed to get the timing stable on all the CPU's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * we have to worry about.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/export.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/sched.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/timex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/preempt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <asm/processor.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <asm/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <asm/timer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <asm/mwait.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #ifdef CONFIG_SMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) # include <asm/smp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) static void delay_loop(u64 __loops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * Calibration and selection of the delay mechanism happens only once
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * during boot.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) static void (*delay_fn)(u64) __ro_after_init = delay_loop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) static void (*delay_halt_fn)(u64 start, u64 cycles) __ro_after_init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) /* simple loop based delay: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) static void delay_loop(u64 __loops)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) unsigned long loops = (unsigned long)__loops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) asm volatile(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) " test %0,%0 \n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) " jz 3f \n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) " jmp 1f \n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) ".align 16 \n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) "1: jmp 2f \n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) ".align 16 \n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) "2: dec %0 \n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) " jnz 2b \n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) "3: dec %0 \n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) : /* we don't need output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) :"a" (loops)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) /* TSC based delay: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) static void delay_tsc(u64 cycles)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) u64 bclock, now;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) int cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) preempt_disable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) cpu = smp_processor_id();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) bclock = rdtsc_ordered();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) for (;;) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) now = rdtsc_ordered();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) if ((now - bclock) >= cycles)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) /* Allow RT tasks to run */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) preempt_enable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) rep_nop();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) preempt_disable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) * It is possible that we moved to another CPU, and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) * since TSC's are per-cpu we need to calculate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) * that. The delay must guarantee that we wait "at
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) * least" the amount of time. Being moved to another
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) * CPU could make the wait longer but we just need to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) * make sure we waited long enough. Rebalance the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) * counter for this CPU.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) if (unlikely(cpu != smp_processor_id())) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) cycles -= (now - bclock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) cpu = smp_processor_id();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) bclock = rdtsc_ordered();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) preempt_enable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) * On Intel the TPAUSE instruction waits until any of:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) * 1) the TSC counter exceeds the value provided in EDX:EAX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) * 2) global timeout in IA32_UMWAIT_CONTROL is exceeded
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) * 3) an external interrupt occurs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) static void delay_halt_tpause(u64 start, u64 cycles)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) u64 until = start + cycles;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) u32 eax, edx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) eax = lower_32_bits(until);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) edx = upper_32_bits(until);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) * Hard code the deeper (C0.2) sleep state because exit latency is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) * small compared to the "microseconds" that usleep() will delay.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) __tpause(TPAUSE_C02_STATE, edx, eax);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) * On some AMD platforms, MWAITX has a configurable 32-bit timer, that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) * counts with TSC frequency. The input value is the number of TSC cycles
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) * to wait. MWAITX will also exit when the timer expires.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) static void delay_halt_mwaitx(u64 unused, u64 cycles)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) u64 delay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) delay = min_t(u64, MWAITX_MAX_WAIT_CYCLES, cycles);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) * Use cpu_tss_rw as a cacheline-aligned, seldomly accessed per-cpu
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) * variable as the monitor target.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) __monitorx(raw_cpu_ptr(&cpu_tss_rw), 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) * AMD, like Intel, supports the EAX hint and EAX=0xf means, do not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) * enter any deep C-state and we use it here in delay() to minimize
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) * wakeup latency.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) __mwaitx(MWAITX_DISABLE_CSTATES, delay, MWAITX_ECX_TIMER_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) * Call a vendor specific function to delay for a given amount of time. Because
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) * these functions may return earlier than requested, check for actual elapsed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) * time and call again until done.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) static void delay_halt(u64 __cycles)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) u64 start, end, cycles = __cycles;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) * Timer value of 0 causes MWAITX to wait indefinitely, unless there
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) * is a store on the memory monitored by MONITORX.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) if (!cycles)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) start = rdtsc_ordered();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) for (;;) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) delay_halt_fn(start, cycles);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) end = rdtsc_ordered();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) if (cycles <= end - start)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) cycles -= end - start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) start = end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) void __init use_tsc_delay(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) if (delay_fn == delay_loop)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) delay_fn = delay_tsc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) void __init use_tpause_delay(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) delay_halt_fn = delay_halt_tpause;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) delay_fn = delay_halt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) void use_mwaitx_delay(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) delay_halt_fn = delay_halt_mwaitx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) delay_fn = delay_halt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) int read_current_timer(unsigned long *timer_val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) if (delay_fn == delay_tsc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) *timer_val = rdtsc();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) void __delay(unsigned long loops)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) delay_fn(loops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) EXPORT_SYMBOL(__delay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) noinline void __const_udelay(unsigned long xloops)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) unsigned long lpj = this_cpu_read(cpu_info.loops_per_jiffy) ? : loops_per_jiffy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) int d0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) xloops *= 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) asm("mull %%edx"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) :"=d" (xloops), "=&a" (d0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) :"1" (xloops), "0" (lpj * (HZ / 4)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) __delay(++xloops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) EXPORT_SYMBOL(__const_udelay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) void __udelay(unsigned long usecs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) __const_udelay(usecs * 0x000010c7); /* 2**32 / 1000000 (rounded up) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) EXPORT_SYMBOL(__udelay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) void __ndelay(unsigned long nsecs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) __const_udelay(nsecs * 0x00005); /* 2**32 / 1000000000 (rounded up) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) EXPORT_SYMBOL(__ndelay);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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