Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) #ifndef __KVM_X86_VMX_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3) #define __KVM_X86_VMX_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) #include <linux/kvm_host.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #include <asm/kvm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <asm/intel_pt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include "capabilities.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include "kvm_cache_regs.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include "posted_intr.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include "vmcs.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include "vmx_ops.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include "cpuid.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) extern const u32 vmx_msr_index[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define MSR_TYPE_R	1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define MSR_TYPE_W	2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define MSR_TYPE_RW	3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define X2APIC_MSR(r) (APIC_BASE_MSR + ((r) >> 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #ifdef CONFIG_X86_64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define MAX_NR_USER_RETURN_MSRS	7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define MAX_NR_USER_RETURN_MSRS	4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define MAX_NR_LOADSTORE_MSRS	8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) struct vmx_msrs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	unsigned int		nr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	struct vmx_msr_entry	val[MAX_NR_LOADSTORE_MSRS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) struct vmx_uret_msr {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	unsigned int slot; /* The MSR's slot in kvm_user_return_msrs. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	u64 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	u64 mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) enum segment_cache_field {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	SEG_FIELD_SEL = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	SEG_FIELD_BASE = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	SEG_FIELD_LIMIT = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	SEG_FIELD_AR = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	SEG_FIELD_NR = 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define RTIT_ADDR_RANGE		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) struct pt_ctx {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	u64 ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	u64 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	u64 output_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	u64 output_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	u64 cr3_match;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	u64 addr_a[RTIT_ADDR_RANGE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	u64 addr_b[RTIT_ADDR_RANGE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) struct pt_desc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	u64 ctl_bitmask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	u32 addr_range;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	u32 caps[PT_CPUID_REGS_NUM * PT_CPUID_LEAVES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	struct pt_ctx host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	struct pt_ctx guest;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) union vmx_exit_reason {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 		u32	basic			: 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 		u32	reserved16		: 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 		u32	reserved17		: 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 		u32	reserved18		: 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 		u32	reserved19		: 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 		u32	reserved20		: 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 		u32	reserved21		: 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 		u32	reserved22		: 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 		u32	reserved23		: 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 		u32	reserved24		: 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 		u32	reserved25		: 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 		u32	reserved26		: 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 		u32	enclave_mode		: 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 		u32	smi_pending_mtf		: 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 		u32	smi_from_vmx_root	: 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 		u32	reserved30		: 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 		u32	failed_vmentry		: 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	u32 full;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97)  * The nested_vmx structure is part of vcpu_vmx, and holds information we need
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98)  * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) struct nested_vmx {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	/* Has the level1 guest done vmxon? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	bool vmxon;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	gpa_t vmxon_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	bool pml_full;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	/* The guest-physical address of the current VMCS L1 keeps for L2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	gpa_t current_vmptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	 * Cache of the guest's VMCS, existing outside of guest memory.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	 * Loaded from guest memory during VMPTRLD. Flushed to guest
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	 * memory during VMCLEAR and VMPTRLD.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	struct vmcs12 *cached_vmcs12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	 * Cache of the guest's shadow VMCS, existing outside of guest
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	 * memory. Loaded from guest memory during VM entry. Flushed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	 * to guest memory during VM exit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	struct vmcs12 *cached_shadow_vmcs12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	 * Indicates if the shadow vmcs or enlightened vmcs must be updated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	 * with the data held by struct vmcs12.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	bool need_vmcs12_to_shadow_sync;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	bool dirty_vmcs12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	 * Indicates lazily loaded guest state has not yet been decached from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	 * vmcs02.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	bool need_sync_vmcs02_to_vmcs12_rare;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	 * vmcs02 has been initialized, i.e. state that is constant for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	 * vmcs02 has been written to the backing VMCS.  Initialization
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	 * is delayed until L1 actually attempts to run a nested VM.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	bool vmcs02_initialized;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	bool change_vmcs01_virtual_apic_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	bool reload_vmcs01_apic_access_page;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	 * Enlightened VMCS has been enabled. It does not mean that L1 has to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	 * use it. However, VMX features available to L1 will be limited based
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	 * on what the enlightened VMCS supports.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	bool enlightened_vmcs_enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	/* L2 must run next, and mustn't decide to exit to L1. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	bool nested_run_pending;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	/* Pending MTF VM-exit into L1.  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	bool mtf_pending;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	struct loaded_vmcs vmcs02;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	 * Guest pages referred to in the vmcs02 with host-physical
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	 * pointers, so we must keep them pinned while L2 runs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	struct page *apic_access_page;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	struct kvm_host_map virtual_apic_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	struct kvm_host_map pi_desc_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	struct kvm_host_map msr_bitmap_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	struct pi_desc *pi_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	bool pi_pending;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	u16 posted_intr_nv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	struct hrtimer preemption_timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	u64 preemption_timer_deadline;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	bool has_preemption_timer_deadline;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	bool preemption_timer_expired;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	/* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	u64 vmcs01_debugctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	u64 vmcs01_guest_bndcfgs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	/* to migrate it to L1 if L2 writes to L1's CR8 directly */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	int l1_tpr_threshold;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	u16 vpid02;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	u16 last_vpid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	struct nested_vmx_msrs msrs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	/* SMM related state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 		/* in VMX operation on SMM entry? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 		bool vmxon;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 		/* in guest mode on SMM entry? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 		bool guest_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	} smm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	gpa_t hv_evmcs_vmptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	struct kvm_host_map hv_evmcs_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	struct hv_enlightened_vmcs *hv_evmcs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) struct vcpu_vmx {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	struct kvm_vcpu       vcpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	u8                    fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	u8		      msr_bitmap_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	 * If true, host state has been stored in vmx->loaded_vmcs for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	 * the CPU registers that only need to be switched when transitioning
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	 * to/from the kernel, and the registers have been loaded with guest
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	 * values.  If false, host state is loaded in the CPU registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	 * and vmx->loaded_vmcs->host_state is invalid.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	bool		      guest_state_loaded;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	unsigned long         exit_qualification;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	u32                   exit_intr_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	u32                   idt_vectoring_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	ulong                 rflags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	struct vmx_uret_msr   guest_uret_msrs[MAX_NR_USER_RETURN_MSRS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	int                   nr_uret_msrs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	int                   nr_active_uret_msrs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	bool                  guest_uret_msrs_loaded;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #ifdef CONFIG_X86_64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	u64		      msr_host_kernel_gs_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	u64		      msr_guest_kernel_gs_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	u64		      spec_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	u32		      msr_ia32_umwait_control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	u32 secondary_exec_control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	 * non-nested (L1) guest, it always points to vmcs01. For a nested
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	 * guest (L2), it points to a different VMCS.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	struct loaded_vmcs    vmcs01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	struct loaded_vmcs   *loaded_vmcs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	struct msr_autoload {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 		struct vmx_msrs guest;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 		struct vmx_msrs host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	} msr_autoload;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	struct msr_autostore {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 		struct vmx_msrs guest;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	} msr_autostore;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 		int vm86_active;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 		ulong save_rflags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 		struct kvm_segment segs[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	} rmode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 		u32 bitmask; /* 4 bits per segment (1 bit per field) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 		struct kvm_save_segment {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 			u16 selector;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 			unsigned long base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 			u32 limit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 			u32 ar;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 		} seg[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	} segment_cache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	int vpid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	bool emulation_required;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	union vmx_exit_reason exit_reason;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	/* Posted interrupt descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	struct pi_desc pi_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	/* Support for a guest hypervisor (nested VMX) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	struct nested_vmx nested;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	/* Dynamic PLE window. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	unsigned int ple_window;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	bool ple_window_dirty;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	bool req_immediate_exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	/* Support for PML */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define PML_ENTITY_NUM		512
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	struct page *pml_pg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	/* apic deadline value in host tsc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	u64 hv_deadline_tsc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	u64 current_tsc_ratio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	unsigned long host_debugctlmsr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	 * Only bits masked by msr_ia32_feature_control_valid_bits can be set in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	 * msr_ia32_feature_control. FEAT_CTL_LOCKED is always included
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	 * in msr_ia32_feature_control_valid_bits.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	u64 msr_ia32_feature_control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	u64 msr_ia32_feature_control_valid_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	u64 ept_pointer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	struct pt_desc pt_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	/* Save desired MSR intercept (read: pass-through) state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #define MAX_POSSIBLE_PASSTHROUGH_MSRS	13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 		DECLARE_BITMAP(read, MAX_POSSIBLE_PASSTHROUGH_MSRS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 		DECLARE_BITMAP(write, MAX_POSSIBLE_PASSTHROUGH_MSRS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	} shadow_msr_intercept;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) enum ept_pointers_status {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	EPT_POINTERS_CHECK = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	EPT_POINTERS_MATCH = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	EPT_POINTERS_MISMATCH = 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) struct kvm_vmx {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	struct kvm kvm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 	unsigned int tss_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	bool ept_identity_pagetable_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 	gpa_t ept_identity_map_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	enum ept_pointers_status ept_pointers_match;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	spinlock_t ept_pointer_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) bool nested_vmx_allowed(struct kvm_vcpu *vcpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) void vmx_vcpu_load_vmcs(struct kvm_vcpu *vcpu, int cpu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 			struct loaded_vmcs *buddy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) int allocate_vpid(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) void free_vpid(int vpid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) void vmx_set_constant_host_state(struct vcpu_vmx *vmx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) void vmx_prepare_switch_to_guest(struct kvm_vcpu *vcpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) void vmx_set_host_fs_gs(struct vmcs_host_state *host, u16 fs_sel, u16 gs_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 			unsigned long fs_base, unsigned long gs_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) int vmx_get_cpl(struct kvm_vcpu *vcpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) int vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) void set_cr4_guest_host_mask(struct vcpu_vmx *vmx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) void ept_save_pdptrs(struct kvm_vcpu *vcpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) void vmx_get_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) void vmx_set_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) u64 construct_eptp(struct kvm_vcpu *vcpu, unsigned long root_hpa,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 		   int root_level);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) bool vmx_guest_inject_ac(struct kvm_vcpu *vcpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) void update_exception_bitmap(struct kvm_vcpu *vcpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) void vmx_update_msr_bitmap(struct kvm_vcpu *vcpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) bool vmx_nmi_blocked(struct kvm_vcpu *vcpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) bool vmx_interrupt_blocked(struct kvm_vcpu *vcpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) void vmx_set_virtual_apic_mode(struct kvm_vcpu *vcpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) struct vmx_uret_msr *vmx_find_uret_msr(struct vcpu_vmx *vmx, u32 msr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) void pt_update_intercept_for_msr(struct kvm_vcpu *vcpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) void vmx_update_host_rsp(struct vcpu_vmx *vmx, unsigned long host_rsp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) int vmx_find_loadstore_msr_slot(struct vmx_msrs *m, u32 msr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) void vmx_ept_load_pdptrs(struct kvm_vcpu *vcpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) static inline u8 vmx_get_rvi(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 	return vmcs_read16(GUEST_INTR_STATUS) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) #define BUILD_CONTROLS_SHADOW(lname, uname)				    \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) static inline void lname##_controls_set(struct vcpu_vmx *vmx, u32 val)	    \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) {									    \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 	if (vmx->loaded_vmcs->controls_shadow.lname != val) {		    \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 		vmcs_write32(uname, val);				    \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 		vmx->loaded_vmcs->controls_shadow.lname = val;		    \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 	}								    \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) }									    \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) static inline u32 lname##_controls_get(struct vcpu_vmx *vmx)		    \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) {									    \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 	return vmx->loaded_vmcs->controls_shadow.lname;			    \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) }									    \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) static inline void lname##_controls_setbit(struct vcpu_vmx *vmx, u32 val)   \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) {									    \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 	lname##_controls_set(vmx, lname##_controls_get(vmx) | val);	    \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) }									    \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) static inline void lname##_controls_clearbit(struct vcpu_vmx *vmx, u32 val) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) {									    \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 	lname##_controls_set(vmx, lname##_controls_get(vmx) & ~val);	    \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) BUILD_CONTROLS_SHADOW(vm_entry, VM_ENTRY_CONTROLS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) BUILD_CONTROLS_SHADOW(vm_exit, VM_EXIT_CONTROLS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) BUILD_CONTROLS_SHADOW(pin, PIN_BASED_VM_EXEC_CONTROL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) BUILD_CONTROLS_SHADOW(exec, CPU_BASED_VM_EXEC_CONTROL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) BUILD_CONTROLS_SHADOW(secondary_exec, SECONDARY_VM_EXEC_CONTROL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) static inline void vmx_register_cache_reset(struct kvm_vcpu *vcpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 	vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 				  | (1 << VCPU_EXREG_RFLAGS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 				  | (1 << VCPU_EXREG_PDPTR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 				  | (1 << VCPU_EXREG_SEGMENTS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 				  | (1 << VCPU_EXREG_CR0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 				  | (1 << VCPU_EXREG_CR3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 				  | (1 << VCPU_EXREG_CR4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 				  | (1 << VCPU_EXREG_EXIT_INFO_1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 				  | (1 << VCPU_EXREG_EXIT_INFO_2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 	vcpu->arch.regs_dirty = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) static inline u32 vmx_vmentry_ctrl(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 	u32 vmentry_ctrl = vmcs_config.vmentry_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 	if (vmx_pt_mode_is_system())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) 		vmentry_ctrl &= ~(VM_ENTRY_PT_CONCEAL_PIP |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 				  VM_ENTRY_LOAD_IA32_RTIT_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 	/* Loading of EFER and PERF_GLOBAL_CTRL are toggled dynamically */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 	return vmentry_ctrl &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) 		~(VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VM_ENTRY_LOAD_IA32_EFER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) static inline u32 vmx_vmexit_ctrl(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) 	u32 vmexit_ctrl = vmcs_config.vmexit_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) 	if (vmx_pt_mode_is_system())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) 		vmexit_ctrl &= ~(VM_EXIT_PT_CONCEAL_PIP |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) 				 VM_EXIT_CLEAR_IA32_RTIT_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) 	/* Loading of EFER and PERF_GLOBAL_CTRL are toggled dynamically */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) 	return vmexit_ctrl &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) 		~(VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | VM_EXIT_LOAD_IA32_EFER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) u32 vmx_exec_control(struct vcpu_vmx *vmx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) static inline struct kvm_vmx *to_kvm_vmx(struct kvm *kvm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) 	return container_of(kvm, struct kvm_vmx, kvm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) 	return container_of(vcpu, struct vcpu_vmx, vcpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) static inline unsigned long vmx_get_exit_qual(struct kvm_vcpu *vcpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) 	struct vcpu_vmx *vmx = to_vmx(vcpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) 	if (!kvm_register_is_available(vcpu, VCPU_EXREG_EXIT_INFO_1)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) 		kvm_register_mark_available(vcpu, VCPU_EXREG_EXIT_INFO_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) 		vmx->exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) 	return vmx->exit_qualification;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) static inline u32 vmx_get_intr_info(struct kvm_vcpu *vcpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) 	struct vcpu_vmx *vmx = to_vmx(vcpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) 	if (!kvm_register_is_available(vcpu, VCPU_EXREG_EXIT_INFO_2)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) 		kvm_register_mark_available(vcpu, VCPU_EXREG_EXIT_INFO_2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) 		vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) 	return vmx->exit_intr_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) struct vmcs *alloc_vmcs_cpu(bool shadow, int cpu, gfp_t flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) void free_vmcs(struct vmcs *vmcs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) int alloc_loaded_vmcs(struct loaded_vmcs *loaded_vmcs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) static inline struct vmcs *alloc_vmcs(bool shadow)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) 	return alloc_vmcs_cpu(shadow, raw_smp_processor_id(),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) 			      GFP_KERNEL_ACCOUNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) static inline void decache_tsc_multiplier(struct vcpu_vmx *vmx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) 	vmx->current_tsc_ratio = vmx->vcpu.arch.tsc_scaling_ratio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) 	vmcs_write64(TSC_MULTIPLIER, vmx->current_tsc_ratio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) static inline bool vmx_has_waitpkg(struct vcpu_vmx *vmx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) 	return secondary_exec_controls_get(vmx) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) 		SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) static inline bool vmx_need_pf_intercept(struct kvm_vcpu *vcpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) 	if (!enable_ept)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) 		return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) 	return allow_smaller_maxphyaddr && cpuid_maxphyaddr(vcpu) < boot_cpu_data.x86_phys_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) static inline bool is_unrestricted_guest(struct kvm_vcpu *vcpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) 	return enable_unrestricted_guest && (!is_guest_mode(vcpu) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) 	    (secondary_exec_controls_get(to_vmx(vcpu)) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) 	    SECONDARY_EXEC_UNRESTRICTED_GUEST));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) bool __vmx_guest_state_valid(struct kvm_vcpu *vcpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) static inline bool vmx_guest_state_valid(struct kvm_vcpu *vcpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) 	return is_unrestricted_guest(vcpu) || __vmx_guest_state_valid(vcpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) void dump_vmcs(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) #endif /* __KVM_X86_VMX_H */