^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) #ifndef KVM_X86_MMU_SPTE_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) #define KVM_X86_MMU_SPTE_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include "mmu_internal.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #define PT_FIRST_AVAIL_BITS_SHIFT 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define PT64_SECOND_AVAIL_BITS_SHIFT 54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * The mask used to denote special SPTEs, which can be either MMIO SPTEs or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * Access Tracking SPTEs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define SPTE_SPECIAL_MASK (3ULL << 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define SPTE_AD_ENABLED_MASK (0ULL << 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define SPTE_AD_DISABLED_MASK (1ULL << 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define SPTE_AD_WRPROT_ONLY_MASK (2ULL << 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define SPTE_MMIO_MASK (3ULL << 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #ifdef CONFIG_DYNAMIC_PHYSICAL_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define PT64_BASE_ADDR_MASK (physical_mask & ~(u64)(PAGE_SIZE-1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define PT64_BASE_ADDR_MASK (((1ULL << 52) - 1) & ~(u64)(PAGE_SIZE-1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define PT64_PERM_MASK (PT_PRESENT_MASK | PT_WRITABLE_MASK | shadow_user_mask \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) | shadow_x_mask | shadow_nx_mask | shadow_me_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define ACC_EXEC_MASK 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define ACC_WRITE_MASK PT_WRITABLE_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define ACC_USER_MASK PT_USER_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define ACC_ALL (ACC_EXEC_MASK | ACC_WRITE_MASK | ACC_USER_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) /* The mask for the R/X bits in EPT PTEs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define PT64_EPT_READABLE_MASK 0x1ull
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define PT64_EPT_EXECUTABLE_MASK 0x4ull
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define PT64_LEVEL_BITS 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define PT64_LEVEL_SHIFT(level) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) (PAGE_SHIFT + (level - 1) * PT64_LEVEL_BITS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define PT64_INDEX(address, level)\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) (((address) >> PT64_LEVEL_SHIFT(level)) & ((1 << PT64_LEVEL_BITS) - 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define SHADOW_PT_INDEX(addr, level) PT64_INDEX(addr, level)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define SPTE_HOST_WRITEABLE (1ULL << PT_FIRST_AVAIL_BITS_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define SPTE_MMU_WRITEABLE (1ULL << (PT_FIRST_AVAIL_BITS_SHIFT + 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * Due to limited space in PTEs, the MMIO generation is a 18 bit subset of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * the memslots generation and is derived as follows:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * Bits 0-8 of the MMIO generation are propagated to spte bits 3-11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) * Bits 9-17 of the MMIO generation are propagated to spte bits 54-62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * The KVM_MEMSLOT_GEN_UPDATE_IN_PROGRESS flag is intentionally not included in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) * the MMIO generation number, as doing so would require stealing a bit from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * the "real" generation number and thus effectively halve the maximum number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * of MMIO generations that can be handled before encountering a wrap (which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) * requires a full MMU zap). The flag is instead explicitly queried when
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * checking for MMIO spte cache hits.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define MMIO_SPTE_GEN_LOW_START 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define MMIO_SPTE_GEN_LOW_END 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define MMIO_SPTE_GEN_HIGH_START PT64_SECOND_AVAIL_BITS_SHIFT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define MMIO_SPTE_GEN_HIGH_END 62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define MMIO_SPTE_GEN_LOW_MASK GENMASK_ULL(MMIO_SPTE_GEN_LOW_END, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) MMIO_SPTE_GEN_LOW_START)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define MMIO_SPTE_GEN_HIGH_MASK GENMASK_ULL(MMIO_SPTE_GEN_HIGH_END, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) MMIO_SPTE_GEN_HIGH_START)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define MMIO_SPTE_GEN_LOW_BITS (MMIO_SPTE_GEN_LOW_END - MMIO_SPTE_GEN_LOW_START + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define MMIO_SPTE_GEN_HIGH_BITS (MMIO_SPTE_GEN_HIGH_END - MMIO_SPTE_GEN_HIGH_START + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) /* remember to adjust the comment above as well if you change these */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) static_assert(MMIO_SPTE_GEN_LOW_BITS == 9 && MMIO_SPTE_GEN_HIGH_BITS == 9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define MMIO_SPTE_GEN_LOW_SHIFT (MMIO_SPTE_GEN_LOW_START - 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define MMIO_SPTE_GEN_HIGH_SHIFT (MMIO_SPTE_GEN_HIGH_START - MMIO_SPTE_GEN_LOW_BITS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define MMIO_SPTE_GEN_MASK GENMASK_ULL(MMIO_SPTE_GEN_LOW_BITS + MMIO_SPTE_GEN_HIGH_BITS - 1, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) extern u64 __read_mostly shadow_nx_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) extern u64 __read_mostly shadow_x_mask; /* mutual exclusive with nx_mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) extern u64 __read_mostly shadow_user_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) extern u64 __read_mostly shadow_accessed_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) extern u64 __read_mostly shadow_dirty_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) extern u64 __read_mostly shadow_mmio_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) extern u64 __read_mostly shadow_mmio_access_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) extern u64 __read_mostly shadow_present_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) extern u64 __read_mostly shadow_me_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) * SPTEs used by MMUs without A/D bits are marked with SPTE_AD_DISABLED_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) * shadow_acc_track_mask is the set of bits to be cleared in non-accessed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) * pages.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) extern u64 __read_mostly shadow_acc_track_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) * This mask must be set on all non-zero Non-Present or Reserved SPTEs in order
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) * to guard against L1TF attacks.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) extern u64 __read_mostly shadow_nonpresent_or_rsvd_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) * The number of high-order 1 bits to use in the mask above.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define SHADOW_NONPRESENT_OR_RSVD_MASK_LEN 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) * The mask/shift to use for saving the original R/X bits when marking the PTE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) * as not-present for access tracking purposes. We do not save the W bit as the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) * PTEs being access tracked also need to be dirty tracked, so the W bit will be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) * restored only when a write is attempted to the page.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define SHADOW_ACC_TRACK_SAVED_BITS_MASK (PT64_EPT_READABLE_MASK | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) PT64_EPT_EXECUTABLE_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define SHADOW_ACC_TRACK_SAVED_BITS_SHIFT PT64_SECOND_AVAIL_BITS_SHIFT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) * In some cases, we need to preserve the GFN of a non-present or reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) * SPTE when we usurp the upper five bits of the physical address space to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) * defend against L1TF, e.g. for MMIO SPTEs. To preserve the GFN, we'll
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) * shift bits of the GFN that overlap with shadow_nonpresent_or_rsvd_mask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) * left into the reserved bits, i.e. the GFN in the SPTE will be split into
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) * high and low parts. This mask covers the lower bits of the GFN.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) extern u64 __read_mostly shadow_nonpresent_or_rsvd_lower_gfn_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) * The number of non-reserved physical address bits irrespective of features
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) * that repurpose legal bits, e.g. MKTME.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) extern u8 __read_mostly shadow_phys_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) static inline bool is_mmio_spte(u64 spte)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) return (spte & SPTE_SPECIAL_MASK) == SPTE_MMIO_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) static inline bool sp_ad_disabled(struct kvm_mmu_page *sp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) return sp->role.ad_disabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) static inline bool spte_ad_enabled(u64 spte)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) MMU_WARN_ON(is_mmio_spte(spte));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) return (spte & SPTE_SPECIAL_MASK) != SPTE_AD_DISABLED_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) static inline bool spte_ad_need_write_protect(u64 spte)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) MMU_WARN_ON(is_mmio_spte(spte));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) return (spte & SPTE_SPECIAL_MASK) != SPTE_AD_ENABLED_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) static inline u64 spte_shadow_accessed_mask(u64 spte)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) MMU_WARN_ON(is_mmio_spte(spte));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) return spte_ad_enabled(spte) ? shadow_accessed_mask : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) static inline u64 spte_shadow_dirty_mask(u64 spte)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) MMU_WARN_ON(is_mmio_spte(spte));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) return spte_ad_enabled(spte) ? shadow_dirty_mask : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) static inline bool is_access_track_spte(u64 spte)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) return !spte_ad_enabled(spte) && (spte & shadow_acc_track_mask) == 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) static inline int is_shadow_present_pte(u64 pte)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) return (pte != 0) && !is_mmio_spte(pte);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) static inline int is_large_pte(u64 pte)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) return pte & PT_PAGE_SIZE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) static inline int is_last_spte(u64 pte, int level)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) if (level == PG_LEVEL_4K)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) if (is_large_pte(pte))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) static inline bool is_executable_pte(u64 spte)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) return (spte & (shadow_x_mask | shadow_nx_mask)) == shadow_x_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) static inline kvm_pfn_t spte_to_pfn(u64 pte)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) return (pte & PT64_BASE_ADDR_MASK) >> PAGE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) static inline bool is_accessed_spte(u64 spte)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) u64 accessed_mask = spte_shadow_accessed_mask(spte);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) return accessed_mask ? spte & accessed_mask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) : !is_access_track_spte(spte);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) static inline bool is_dirty_spte(u64 spte)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) u64 dirty_mask = spte_shadow_dirty_mask(spte);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) return dirty_mask ? spte & dirty_mask : spte & PT_WRITABLE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) static inline bool spte_can_locklessly_be_made_writable(u64 spte)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) return (spte & (SPTE_HOST_WRITEABLE | SPTE_MMU_WRITEABLE)) ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) (SPTE_HOST_WRITEABLE | SPTE_MMU_WRITEABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) static inline u64 get_mmio_spte_generation(u64 spte)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) u64 gen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) gen = (spte & MMIO_SPTE_GEN_LOW_MASK) >> MMIO_SPTE_GEN_LOW_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) gen |= (spte & MMIO_SPTE_GEN_HIGH_MASK) >> MMIO_SPTE_GEN_HIGH_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) return gen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) /* Bits which may be returned by set_spte() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define SET_SPTE_WRITE_PROTECTED_PT BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define SET_SPTE_NEED_REMOTE_TLB_FLUSH BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define SET_SPTE_SPURIOUS BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) int make_spte(struct kvm_vcpu *vcpu, unsigned int pte_access, int level,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) gfn_t gfn, kvm_pfn_t pfn, u64 old_spte, bool speculative,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) bool can_unsync, bool host_writable, bool ad_disabled,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) u64 *new_spte);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) u64 make_nonleaf_spte(u64 *child_pt, bool ad_disabled);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) u64 make_mmio_spte(struct kvm_vcpu *vcpu, u64 gfn, unsigned int access);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) u64 mark_spte_for_access_track(u64 spte);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) u64 kvm_mmu_changed_pte_notifier_make_spte(u64 old_spte, kvm_pfn_t new_pfn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) void kvm_mmu_reset_all_pte_masks(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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