Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) #ifndef __KVM_X86_LAPIC_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3) #define __KVM_X86_LAPIC_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) #include <kvm/iodev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #include <linux/kvm_host.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #define KVM_APIC_INIT		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #define KVM_APIC_SIPI		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #define KVM_APIC_LVT_NUM	6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #define APIC_SHORT_MASK			0xc0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #define APIC_DEST_NOSHORT		0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #define APIC_DEST_MASK			0x800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #define APIC_BUS_CYCLE_NS       1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define APIC_BUS_FREQUENCY      (1000000000ULL / APIC_BUS_CYCLE_NS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define APIC_BROADCAST			0xFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define X2APIC_BROADCAST		0xFFFFFFFFul
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) enum lapic_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 	LAPIC_MODE_DISABLED = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 	LAPIC_MODE_INVALID = X2APIC_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 	LAPIC_MODE_XAPIC = MSR_IA32_APICBASE_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 	LAPIC_MODE_X2APIC = MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) struct kvm_timer {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	struct hrtimer timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 	s64 period; 				/* unit: ns */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	ktime_t target_expiration;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	u32 timer_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	u32 timer_mode_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	u64 tscdeadline;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	u64 expired_tscdeadline;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	u32 timer_advance_ns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	s64 advance_expire_delta;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	atomic_t pending;			/* accumulated triggered timers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	bool hv_timer_in_use;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) struct kvm_lapic {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	unsigned long base_address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	struct kvm_io_device dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	struct kvm_timer lapic_timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	u32 divide_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	struct kvm_vcpu *vcpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	bool sw_enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	bool irr_pending;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	bool lvt0_in_nmi_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	/* Number of bits set in ISR. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	s16 isr_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	/* The highest vector set in ISR; if -1 - invalid, must scan ISR. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	int highest_isr_cache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	/**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	 * APIC register page.  The layout matches the register layout seen by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	 * the guest 1:1, because it is accessed by the vmx microcode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	 * Note: Only one register, the TPR, is used by the microcode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	void *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	gpa_t vapic_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	struct gfn_to_hva_cache vapic_cache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	unsigned long pending_events;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	unsigned int sipi_vector;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) struct dest_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) int kvm_create_lapic(struct kvm_vcpu *vcpu, int timer_advance_ns);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) void kvm_free_lapic(struct kvm_vcpu *vcpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) int kvm_apic_has_interrupt(struct kvm_vcpu *vcpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) int kvm_apic_accept_pic_intr(struct kvm_vcpu *vcpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) int kvm_get_apic_interrupt(struct kvm_vcpu *vcpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) void kvm_apic_accept_events(struct kvm_vcpu *vcpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) void kvm_lapic_reset(struct kvm_vcpu *vcpu, bool init_event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) u64 kvm_lapic_get_cr8(struct kvm_vcpu *vcpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) void kvm_lapic_set_tpr(struct kvm_vcpu *vcpu, unsigned long cr8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) void kvm_lapic_set_eoi(struct kvm_vcpu *vcpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) u64 kvm_lapic_get_base(struct kvm_vcpu *vcpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) void kvm_recalculate_apic_map(struct kvm *kvm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) void kvm_apic_set_version(struct kvm_vcpu *vcpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) int kvm_lapic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) int kvm_lapic_reg_read(struct kvm_lapic *apic, u32 offset, int len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 		       void *data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) bool kvm_apic_match_dest(struct kvm_vcpu *vcpu, struct kvm_lapic *source,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 			   int shorthand, unsigned int dest, int dest_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) int kvm_apic_compare_prio(struct kvm_vcpu *vcpu1, struct kvm_vcpu *vcpu2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) void kvm_apic_clear_irr(struct kvm_vcpu *vcpu, int vec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) bool __kvm_apic_update_irr(u32 *pir, void *regs, int *max_irr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) bool kvm_apic_update_irr(struct kvm_vcpu *vcpu, u32 *pir, int *max_irr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) void kvm_apic_update_ppr(struct kvm_vcpu *vcpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) int kvm_apic_set_irq(struct kvm_vcpu *vcpu, struct kvm_lapic_irq *irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 		     struct dest_map *dest_map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) int kvm_apic_local_deliver(struct kvm_lapic *apic, int lvt_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) void kvm_apic_update_apicv(struct kvm_vcpu *vcpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) bool kvm_irq_delivery_to_apic_fast(struct kvm *kvm, struct kvm_lapic *src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 		struct kvm_lapic_irq *irq, int *r, struct dest_map *dest_map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) void kvm_apic_send_ipi(struct kvm_lapic *apic, u32 icr_low, u32 icr_high);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) u64 kvm_get_apic_base(struct kvm_vcpu *vcpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) int kvm_apic_get_state(struct kvm_vcpu *vcpu, struct kvm_lapic_state *s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) int kvm_apic_set_state(struct kvm_vcpu *vcpu, struct kvm_lapic_state *s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) enum lapic_mode kvm_get_apic_mode(struct kvm_vcpu *vcpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) int kvm_lapic_find_highest_irr(struct kvm_vcpu *vcpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) u64 kvm_get_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) void kvm_set_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu, u64 data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) void kvm_apic_write_nodecode(struct kvm_vcpu *vcpu, u32 offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) void kvm_apic_set_eoi_accelerated(struct kvm_vcpu *vcpu, int vector);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) int kvm_lapic_set_vapic_addr(struct kvm_vcpu *vcpu, gpa_t vapic_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) void kvm_lapic_sync_from_vapic(struct kvm_vcpu *vcpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) void kvm_lapic_sync_to_vapic(struct kvm_vcpu *vcpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) int kvm_x2apic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) int kvm_x2apic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) int kvm_hv_vapic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) int kvm_hv_vapic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) static inline bool kvm_hv_vapic_assist_page_enabled(struct kvm_vcpu *vcpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	return vcpu->arch.hyperv.hv_vapic & HV_X64_MSR_VP_ASSIST_PAGE_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) int kvm_lapic_enable_pv_eoi(struct kvm_vcpu *vcpu, u64 data, unsigned long len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) void kvm_lapic_init(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) void kvm_lapic_exit(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define VEC_POS(v) ((v) & (32 - 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define REG_POS(v) (((v) >> 5) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) static inline void kvm_lapic_clear_vector(int vec, void *bitmap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) static inline void kvm_lapic_set_vector(int vec, void *bitmap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) static inline void kvm_lapic_set_irr(int vec, struct kvm_lapic *apic)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	kvm_lapic_set_vector(vec, apic->regs + APIC_IRR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	 * irr_pending must be true if any interrupt is pending; set it after
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	 * APIC_IRR to avoid race with apic_clear_irr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	apic->irr_pending = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) static inline u32 kvm_lapic_get_reg(struct kvm_lapic *apic, int reg_off)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	return *((u32 *) (apic->regs + reg_off));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) static inline void __kvm_lapic_set_reg(char *regs, int reg_off, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	*((u32 *) (regs + reg_off)) = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) static inline void kvm_lapic_set_reg(struct kvm_lapic *apic, int reg_off, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	__kvm_lapic_set_reg(apic->regs, reg_off, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) extern struct static_key kvm_no_apic_vcpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) static inline bool lapic_in_kernel(struct kvm_vcpu *vcpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	if (static_key_false(&kvm_no_apic_vcpu))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 		return vcpu->arch.apic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) extern struct static_key_deferred apic_hw_disabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) static inline int kvm_apic_hw_enabled(struct kvm_lapic *apic)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	if (static_key_false(&apic_hw_disabled.key))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 		return apic->vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	return MSR_IA32_APICBASE_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) extern struct static_key_deferred apic_sw_disabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) static inline bool kvm_apic_sw_enabled(struct kvm_lapic *apic)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	if (static_key_false(&apic_sw_disabled.key))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 		return apic->sw_enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) static inline bool kvm_apic_present(struct kvm_vcpu *vcpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	return lapic_in_kernel(vcpu) && kvm_apic_hw_enabled(vcpu->arch.apic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) static inline int kvm_lapic_enabled(struct kvm_vcpu *vcpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	return kvm_apic_present(vcpu) && kvm_apic_sw_enabled(vcpu->arch.apic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) static inline int apic_x2apic_mode(struct kvm_lapic *apic)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	return apic->vcpu->arch.apic_base & X2APIC_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) static inline bool kvm_vcpu_apicv_active(struct kvm_vcpu *vcpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	return vcpu->arch.apic && vcpu->arch.apicv_active;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) static inline bool kvm_apic_has_events(struct kvm_vcpu *vcpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	return lapic_in_kernel(vcpu) && vcpu->arch.apic->pending_events;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) static inline bool kvm_lowest_prio_delivery(struct kvm_lapic_irq *irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	return (irq->delivery_mode == APIC_DM_LOWEST ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 			irq->msi_redir_hint);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) static inline int kvm_lapic_latched_init(struct kvm_vcpu *vcpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	return lapic_in_kernel(vcpu) && test_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) bool kvm_apic_pending_eoi(struct kvm_vcpu *vcpu, int vector);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) void kvm_wait_lapic_expire(struct kvm_vcpu *vcpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) void kvm_bitmap_or_dest_vcpus(struct kvm *kvm, struct kvm_lapic_irq *irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 			      unsigned long *vcpu_bitmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) bool kvm_intr_is_single_vcpu_fast(struct kvm *kvm, struct kvm_lapic_irq *irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 			struct kvm_vcpu **dest_vcpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) int kvm_vector_to_index(u32 vector, u32 dest_vcpus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 			const unsigned long *bitmap, u32 bitmap_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) void kvm_lapic_switch_to_sw_timer(struct kvm_vcpu *vcpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) void kvm_lapic_switch_to_hv_timer(struct kvm_vcpu *vcpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) void kvm_lapic_expired_hv_timer(struct kvm_vcpu *vcpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) bool kvm_lapic_hv_timer_in_use(struct kvm_vcpu *vcpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) void kvm_lapic_restart_hv_timer(struct kvm_vcpu *vcpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) bool kvm_can_use_hv_timer(struct kvm_vcpu *vcpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) static inline enum lapic_mode kvm_apic_mode(u64 apic_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	return apic_base & (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) static inline u8 kvm_xapic_id(struct kvm_lapic *apic)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	return kvm_lapic_get_reg(apic, APIC_ID) >> 24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #endif