^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * 8259 interrupt controller emulation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (c) 2003-2004 Fabrice Bellard
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2007 Intel Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright 2009 Red Hat, Inc. and/or its affiliates.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Permission is hereby granted, free of charge, to any person obtaining a copy
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * of this software and associated documentation files (the "Software"), to deal
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * in the Software without restriction, including without limitation the rights
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * copies of the Software, and to permit persons to whom the Software is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * furnished to do so, subject to the following conditions:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * The above copyright notice and this permission notice shall be included in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * all copies or substantial portions of the Software.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * THE SOFTWARE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * Authors:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * Yaozu (Eddie) Dong <Eddie.dong@intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * Port from Qemu.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/mm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include "irq.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <linux/kvm_host.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include "trace.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define pr_pic_unimpl(fmt, ...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) pr_err_ratelimited("kvm: pic: " fmt, ## __VA_ARGS__)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) static void pic_irq_request(struct kvm *kvm, int level);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) static void pic_lock(struct kvm_pic *s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) __acquires(&s->lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) spin_lock(&s->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) static void pic_unlock(struct kvm_pic *s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) __releases(&s->lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) bool wakeup = s->wakeup_needed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) struct kvm_vcpu *vcpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) s->wakeup_needed = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) spin_unlock(&s->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) if (wakeup) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) kvm_for_each_vcpu(i, vcpu, s->kvm) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) if (kvm_apic_accept_pic_intr(vcpu)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) kvm_make_request(KVM_REQ_EVENT, vcpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) kvm_vcpu_kick(vcpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) static void pic_clear_isr(struct kvm_kpic_state *s, int irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) s->isr &= ~(1 << irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) if (s != &s->pics_state->pics[0])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) irq += 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) * We are dropping lock while calling ack notifiers since ack
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) * notifier callbacks for assigned devices call into PIC recursively.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) * Other interrupt may be delivered to PIC while lock is dropped but
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) * it should be safe since PIC state is already updated at this stage.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) pic_unlock(s->pics_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) kvm_notify_acked_irq(s->pics_state->kvm, SELECT_PIC(irq), irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) pic_lock(s->pics_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) * set irq level. If an edge is detected, then the IRR is set to 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) static inline int pic_set_irq1(struct kvm_kpic_state *s, int irq, int level)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) int mask, ret = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) mask = 1 << irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) if (s->elcr & mask) /* level triggered */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) if (level) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) ret = !(s->irr & mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) s->irr |= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) s->last_irr |= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) s->irr &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) s->last_irr &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) else /* edge triggered */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) if (level) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) if ((s->last_irr & mask) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) ret = !(s->irr & mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) s->irr |= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) s->last_irr |= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) s->last_irr &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) return (s->imr & mask) ? -1 : ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) * return the highest priority found in mask (highest = smallest
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) * number). Return 8 if no irq
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) static inline int get_priority(struct kvm_kpic_state *s, int mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) int priority;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) if (mask == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) return 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) priority = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) while ((mask & (1 << ((priority + s->priority_add) & 7))) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) priority++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) return priority;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) * return the pic wanted interrupt. return -1 if none
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) static int pic_get_irq(struct kvm_kpic_state *s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) int mask, cur_priority, priority;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) mask = s->irr & ~s->imr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) priority = get_priority(s, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) if (priority == 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) * compute current priority. If special fully nested mode on the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) * master, the IRQ coming from the slave is not taken into account
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) * for the priority computation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) mask = s->isr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) if (s->special_fully_nested_mode && s == &s->pics_state->pics[0])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) mask &= ~(1 << 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) cur_priority = get_priority(s, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) if (priority < cur_priority)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) * higher priority found: an irq should be generated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) return (priority + s->priority_add) & 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) * raise irq to CPU if necessary. must be called every time the active
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) * irq may change
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) static void pic_update_irq(struct kvm_pic *s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) int irq2, irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) irq2 = pic_get_irq(&s->pics[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) if (irq2 >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) * if irq request by slave pic, signal master PIC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) pic_set_irq1(&s->pics[0], 2, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) pic_set_irq1(&s->pics[0], 2, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) irq = pic_get_irq(&s->pics[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) pic_irq_request(s->kvm, irq >= 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) void kvm_pic_update_irq(struct kvm_pic *s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) pic_lock(s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) pic_update_irq(s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) pic_unlock(s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) int kvm_pic_set_irq(struct kvm_pic *s, int irq, int irq_source_id, int level)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) int ret, irq_level;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) BUG_ON(irq < 0 || irq >= PIC_NUM_PINS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) pic_lock(s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) irq_level = __kvm_irq_line_state(&s->irq_states[irq],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) irq_source_id, level);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) ret = pic_set_irq1(&s->pics[irq >> 3], irq & 7, irq_level);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) pic_update_irq(s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) trace_kvm_pic_set_irq(irq >> 3, irq & 7, s->pics[irq >> 3].elcr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) s->pics[irq >> 3].imr, ret == 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) pic_unlock(s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) void kvm_pic_clear_all(struct kvm_pic *s, int irq_source_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) pic_lock(s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) for (i = 0; i < PIC_NUM_PINS; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) __clear_bit(irq_source_id, &s->irq_states[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) pic_unlock(s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) * acknowledge interrupt 'irq'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) static inline void pic_intack(struct kvm_kpic_state *s, int irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) s->isr |= 1 << irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) * We don't clear a level sensitive interrupt here
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) if (!(s->elcr & (1 << irq)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) s->irr &= ~(1 << irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) if (s->auto_eoi) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) if (s->rotate_on_auto_eoi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) s->priority_add = (irq + 1) & 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) pic_clear_isr(s, irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) int kvm_pic_read_irq(struct kvm *kvm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) int irq, irq2, intno;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) struct kvm_pic *s = kvm->arch.vpic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) s->output = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) pic_lock(s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) irq = pic_get_irq(&s->pics[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) if (irq >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) pic_intack(&s->pics[0], irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) if (irq == 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) irq2 = pic_get_irq(&s->pics[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) if (irq2 >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) pic_intack(&s->pics[1], irq2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) * spurious IRQ on slave controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) irq2 = 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) intno = s->pics[1].irq_base + irq2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) irq = irq2 + 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) intno = s->pics[0].irq_base + irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) * spurious IRQ on host controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) irq = 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) intno = s->pics[0].irq_base + irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) pic_update_irq(s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) pic_unlock(s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) return intno;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) static void kvm_pic_reset(struct kvm_kpic_state *s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) int irq, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) struct kvm_vcpu *vcpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) u8 edge_irr = s->irr & ~s->elcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) bool found = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) s->last_irr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) s->irr &= s->elcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) s->imr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) s->priority_add = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) s->special_mask = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) s->read_reg_select = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) if (!s->init4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) s->special_fully_nested_mode = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) s->auto_eoi = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) s->init_state = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) kvm_for_each_vcpu(i, vcpu, s->pics_state->kvm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) if (kvm_apic_accept_pic_intr(vcpu)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) found = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) if (!found)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) for (irq = 0; irq < PIC_NUM_PINS/2; irq++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) if (edge_irr & (1 << irq))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) pic_clear_isr(s, irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) static void pic_ioport_write(void *opaque, u32 addr, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) struct kvm_kpic_state *s = opaque;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) int priority, cmd, irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) addr &= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) if (addr == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) if (val & 0x10) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) s->init4 = val & 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) if (val & 0x02)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) pr_pic_unimpl("single mode not supported");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) if (val & 0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) pr_pic_unimpl(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) "level sensitive irq not supported");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) kvm_pic_reset(s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) } else if (val & 0x08) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) if (val & 0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) s->poll = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) if (val & 0x02)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) s->read_reg_select = val & 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) if (val & 0x40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) s->special_mask = (val >> 5) & 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) cmd = val >> 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) s->rotate_on_auto_eoi = cmd >> 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) case 1: /* end of interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) case 5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) priority = get_priority(s, s->isr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) if (priority != 8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) irq = (priority + s->priority_add) & 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) if (cmd == 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) s->priority_add = (irq + 1) & 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) pic_clear_isr(s, irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) pic_update_irq(s->pics_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) irq = val & 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) pic_clear_isr(s, irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) pic_update_irq(s->pics_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) case 6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) s->priority_add = (val + 1) & 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) pic_update_irq(s->pics_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) case 7:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) irq = val & 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) s->priority_add = (irq + 1) & 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) pic_clear_isr(s, irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) pic_update_irq(s->pics_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) break; /* no operation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) switch (s->init_state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) case 0: { /* normal mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) u8 imr_diff = s->imr ^ val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) off = (s == &s->pics_state->pics[0]) ? 0 : 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) s->imr = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) for (irq = 0; irq < PIC_NUM_PINS/2; irq++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) if (imr_diff & (1 << irq))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) kvm_fire_mask_notifiers(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) s->pics_state->kvm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) SELECT_PIC(irq + off),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) irq + off,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) !!(s->imr & (1 << irq)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) pic_update_irq(s->pics_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) s->irq_base = val & 0xf8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) s->init_state = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) if (s->init4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) s->init_state = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) s->init_state = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) s->special_fully_nested_mode = (val >> 4) & 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) s->auto_eoi = (val >> 1) & 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) s->init_state = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) static u32 pic_poll_read(struct kvm_kpic_state *s, u32 addr1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) ret = pic_get_irq(s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) if (ret >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) if (addr1 >> 7) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) s->pics_state->pics[0].isr &= ~(1 << 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) s->pics_state->pics[0].irr &= ~(1 << 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) s->irr &= ~(1 << ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) pic_clear_isr(s, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) if (addr1 >> 7 || ret != 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) pic_update_irq(s->pics_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) ret = 0x07;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) pic_update_irq(s->pics_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) static u32 pic_ioport_read(void *opaque, u32 addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) struct kvm_kpic_state *s = opaque;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) if (s->poll) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) ret = pic_poll_read(s, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) s->poll = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) if ((addr & 1) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) if (s->read_reg_select)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) ret = s->isr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) ret = s->irr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) ret = s->imr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) static void elcr_ioport_write(void *opaque, u32 addr, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) struct kvm_kpic_state *s = opaque;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) s->elcr = val & s->elcr_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) static u32 elcr_ioport_read(void *opaque, u32 addr1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) struct kvm_kpic_state *s = opaque;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) return s->elcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) static int picdev_write(struct kvm_pic *s,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) gpa_t addr, int len, const void *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) unsigned char data = *(unsigned char *)val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) if (len != 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) pr_pic_unimpl("non byte write\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) switch (addr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) case 0x20:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) case 0x21:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) pic_lock(s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) pic_ioport_write(&s->pics[0], addr, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) pic_unlock(s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) case 0xa0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) case 0xa1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) pic_lock(s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) pic_ioport_write(&s->pics[1], addr, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) pic_unlock(s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) case 0x4d0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) case 0x4d1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) pic_lock(s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) elcr_ioport_write(&s->pics[addr & 1], addr, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) pic_unlock(s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) static int picdev_read(struct kvm_pic *s,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) gpa_t addr, int len, void *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) unsigned char *data = (unsigned char *)val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) if (len != 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) memset(val, 0, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) pr_pic_unimpl("non byte read\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) switch (addr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) case 0x20:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) case 0x21:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) case 0xa0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) case 0xa1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) pic_lock(s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) *data = pic_ioport_read(&s->pics[addr >> 7], addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) pic_unlock(s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) case 0x4d0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) case 0x4d1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) pic_lock(s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) *data = elcr_ioport_read(&s->pics[addr & 1], addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) pic_unlock(s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) static int picdev_master_write(struct kvm_vcpu *vcpu, struct kvm_io_device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) gpa_t addr, int len, const void *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) return picdev_write(container_of(dev, struct kvm_pic, dev_master),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) addr, len, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) static int picdev_master_read(struct kvm_vcpu *vcpu, struct kvm_io_device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) gpa_t addr, int len, void *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) return picdev_read(container_of(dev, struct kvm_pic, dev_master),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) addr, len, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) static int picdev_slave_write(struct kvm_vcpu *vcpu, struct kvm_io_device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) gpa_t addr, int len, const void *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) return picdev_write(container_of(dev, struct kvm_pic, dev_slave),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) addr, len, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) static int picdev_slave_read(struct kvm_vcpu *vcpu, struct kvm_io_device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) gpa_t addr, int len, void *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) return picdev_read(container_of(dev, struct kvm_pic, dev_slave),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) addr, len, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) static int picdev_eclr_write(struct kvm_vcpu *vcpu, struct kvm_io_device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) gpa_t addr, int len, const void *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) return picdev_write(container_of(dev, struct kvm_pic, dev_eclr),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) addr, len, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) static int picdev_eclr_read(struct kvm_vcpu *vcpu, struct kvm_io_device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) gpa_t addr, int len, void *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) return picdev_read(container_of(dev, struct kvm_pic, dev_eclr),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) addr, len, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) * callback when PIC0 irq status changed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) static void pic_irq_request(struct kvm *kvm, int level)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) struct kvm_pic *s = kvm->arch.vpic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) if (!s->output)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) s->wakeup_needed = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) s->output = level;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) static const struct kvm_io_device_ops picdev_master_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) .read = picdev_master_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) .write = picdev_master_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) static const struct kvm_io_device_ops picdev_slave_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) .read = picdev_slave_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) .write = picdev_slave_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) static const struct kvm_io_device_ops picdev_eclr_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) .read = picdev_eclr_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) .write = picdev_eclr_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) int kvm_pic_init(struct kvm *kvm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) struct kvm_pic *s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) s = kzalloc(sizeof(struct kvm_pic), GFP_KERNEL_ACCOUNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) if (!s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) spin_lock_init(&s->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) s->kvm = kvm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) s->pics[0].elcr_mask = 0xf8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) s->pics[1].elcr_mask = 0xde;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) s->pics[0].pics_state = s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) s->pics[1].pics_state = s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) * Initialize PIO device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) kvm_iodevice_init(&s->dev_master, &picdev_master_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) kvm_iodevice_init(&s->dev_slave, &picdev_slave_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) kvm_iodevice_init(&s->dev_eclr, &picdev_eclr_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) mutex_lock(&kvm->slots_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) ret = kvm_io_bus_register_dev(kvm, KVM_PIO_BUS, 0x20, 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) &s->dev_master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) goto fail_unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) ret = kvm_io_bus_register_dev(kvm, KVM_PIO_BUS, 0xa0, 2, &s->dev_slave);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) goto fail_unreg_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) ret = kvm_io_bus_register_dev(kvm, KVM_PIO_BUS, 0x4d0, 2, &s->dev_eclr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) goto fail_unreg_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) mutex_unlock(&kvm->slots_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) kvm->arch.vpic = s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) fail_unreg_1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS, &s->dev_slave);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) fail_unreg_2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS, &s->dev_master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) fail_unlock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) mutex_unlock(&kvm->slots_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) kfree(s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) void kvm_pic_destroy(struct kvm *kvm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) struct kvm_pic *vpic = kvm->arch.vpic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) if (!vpic)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) mutex_lock(&kvm->slots_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) kvm_io_bus_unregister_dev(vpic->kvm, KVM_PIO_BUS, &vpic->dev_master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) kvm_io_bus_unregister_dev(vpic->kvm, KVM_PIO_BUS, &vpic->dev_slave);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) kvm_io_bus_unregister_dev(vpic->kvm, KVM_PIO_BUS, &vpic->dev_eclr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) mutex_unlock(&kvm->slots_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) kvm->arch.vpic = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) kfree(vpic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags