^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * vSMPowered(tm) systems specific initialization
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2005 ScaleMP Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Ravikiran Thirumalai <kiran@scalemp.com>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Shai Fultheim <shai@scalemp.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Paravirt ops integration: Glauber de Oliveira Costa <gcosta@redhat.com>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Ravikiran Thirumalai <kiran@scalemp.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/pci_ids.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/pci_regs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/smp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <asm/apic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <asm/pci-direct.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <asm/paravirt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <asm/setup.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define TOPOLOGY_REGISTER_OFFSET 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #ifdef CONFIG_PCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) static void __init set_vsmp_ctl(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) void __iomem *address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) unsigned int cap, ctl, cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) /* set vSMP magic bits to indicate vSMP capable kernel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) cfg = read_pci_config(0, 0x1f, 0, PCI_BASE_ADDRESS_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) address = early_ioremap(cfg, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) cap = readl(address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) ctl = readl(address + 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) printk(KERN_INFO "vSMP CTL: capabilities:0x%08x control:0x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) cap, ctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) /* If possible, let the vSMP foundation route the interrupt optimally */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #ifdef CONFIG_SMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) if (cap & ctl & BIT(8)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) ctl &= ~BIT(8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #ifdef CONFIG_PROC_FS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) /* Don't let users change irq affinity via procfs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) no_irq_affinity = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) writel(ctl, address + 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) ctl = readl(address + 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) pr_info("vSMP CTL: control set to:0x%08x\n", ctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) early_iounmap(address, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) static int is_vsmp = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) static void __init detect_vsmp_box(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) is_vsmp = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) if (!early_pci_allowed())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) /* Check if we are running on a ScaleMP vSMPowered box */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) if (read_pci_config(0, 0x1f, 0, PCI_VENDOR_ID) ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) (PCI_VENDOR_ID_SCALEMP | (PCI_DEVICE_ID_SCALEMP_VSMP_CTL << 16)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) is_vsmp = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) static int is_vsmp_box(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) if (is_vsmp != -1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) return is_vsmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) WARN_ON_ONCE(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) static void __init detect_vsmp_box(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) static int is_vsmp_box(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) static void __init set_vsmp_ctl(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) static void __init vsmp_cap_cpus(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #if !defined(CONFIG_X86_VSMP) && defined(CONFIG_SMP) && defined(CONFIG_PCI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) void __iomem *address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) unsigned int cfg, topology, node_shift, maxcpus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) * CONFIG_X86_VSMP is not configured, so limit the number CPUs to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) * ones present in the first board, unless explicitly overridden by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) * setup_max_cpus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) if (setup_max_cpus != NR_CPUS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) /* Read the vSMP Foundation topology register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) cfg = read_pci_config(0, 0x1f, 0, PCI_BASE_ADDRESS_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) address = early_ioremap(cfg + TOPOLOGY_REGISTER_OFFSET, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) if (WARN_ON(!address))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) topology = readl(address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) node_shift = (topology >> 16) & 0x7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) if (!node_shift)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) /* The value 0 should be decoded as 8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) node_shift = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) maxcpus = (topology & ((1 << node_shift) - 1)) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) pr_info("vSMP CTL: Capping CPUs to %d (CONFIG_X86_VSMP is unset)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) maxcpus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) setup_max_cpus = maxcpus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) early_iounmap(address, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) static int apicid_phys_pkg_id(int initial_apic_id, int index_msb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) return hard_smp_processor_id() >> index_msb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) static void vsmp_apic_post_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) /* need to update phys_pkg_id */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) apic->phys_pkg_id = apicid_phys_pkg_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) void __init vsmp_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) detect_vsmp_box();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) if (!is_vsmp_box())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) x86_platform.apic_post_init = vsmp_apic_post_init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) vsmp_cap_cpus();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) set_vsmp_ctl();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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