^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * AMD Encrypted Register State Support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Author: Joerg Roedel <jroedel@suse.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * This file is not compiled stand-alone. It contains code shared
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * between the pre-decompression boot code and the running Linux kernel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * and is included directly into both code-bases.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #ifndef __BOOT_COMPRESSED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define error(v) pr_err(v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define has_cpuflag(f) boot_cpu_has(f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) static bool __init sev_es_check_cpu_features(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) if (!has_cpuflag(X86_FEATURE_RDRAND)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) error("RDRAND instruction not supported - no trusted source of randomness available\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) static void sev_es_terminate(unsigned int reason)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) u64 val = GHCB_SEV_TERMINATE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * Tell the hypervisor what went wrong - only reason-set 0 is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * currently supported.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) val |= GHCB_SEV_TERMINATE_REASON(0, reason);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) /* Request Guest Termination from Hypvervisor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) sev_es_wr_ghcb_msr(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) VMGEXIT();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) while (true)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) asm volatile("hlt\n" : : : "memory");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) static bool sev_es_negotiate_protocol(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) u64 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) /* Do the GHCB protocol version negotiation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) sev_es_wr_ghcb_msr(GHCB_SEV_INFO_REQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) VMGEXIT();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) val = sev_es_rd_ghcb_msr();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) if (GHCB_INFO(val) != GHCB_SEV_INFO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) if (GHCB_PROTO_MAX(val) < GHCB_PROTO_OUR ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) GHCB_PROTO_MIN(val) > GHCB_PROTO_OUR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) static __always_inline void vc_ghcb_invalidate(struct ghcb *ghcb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) ghcb->save.sw_exit_code = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) memset(ghcb->save.valid_bitmap, 0, sizeof(ghcb->save.valid_bitmap));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) static bool vc_decoding_needed(unsigned long exit_code)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) /* Exceptions don't require to decode the instruction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) return !(exit_code >= SVM_EXIT_EXCP_BASE &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) exit_code <= SVM_EXIT_LAST_EXCP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) static enum es_result vc_init_em_ctxt(struct es_em_ctxt *ctxt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) struct pt_regs *regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) unsigned long exit_code)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) enum es_result ret = ES_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) memset(ctxt, 0, sizeof(*ctxt));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) ctxt->regs = regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) if (vc_decoding_needed(exit_code))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) ret = vc_decode_insn(ctxt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) static void vc_finish_insn(struct es_em_ctxt *ctxt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) ctxt->regs->ip += ctxt->insn.length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) static enum es_result sev_es_ghcb_hv_call(struct ghcb *ghcb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) struct es_em_ctxt *ctxt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) u64 exit_code, u64 exit_info_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) u64 exit_info_2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) enum es_result ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) /* Fill in protocol and format specifiers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) ghcb->protocol_version = GHCB_PROTOCOL_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) ghcb->ghcb_usage = GHCB_DEFAULT_USAGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) ghcb_set_sw_exit_code(ghcb, exit_code);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) ghcb_set_sw_exit_info_1(ghcb, exit_info_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) ghcb_set_sw_exit_info_2(ghcb, exit_info_2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) sev_es_wr_ghcb_msr(__pa(ghcb));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) VMGEXIT();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) if ((ghcb->save.sw_exit_info_1 & 0xffffffff) == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) u64 info = ghcb->save.sw_exit_info_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) unsigned long v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) info = ghcb->save.sw_exit_info_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) v = info & SVM_EVTINJ_VEC_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) /* Check if exception information from hypervisor is sane. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) if ((info & SVM_EVTINJ_VALID) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) ((v == X86_TRAP_GP) || (v == X86_TRAP_UD)) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) ((info & SVM_EVTINJ_TYPE_MASK) == SVM_EVTINJ_TYPE_EXEPT)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) ctxt->fi.vector = v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) if (info & SVM_EVTINJ_VALID_ERR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) ctxt->fi.error_code = info >> 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) ret = ES_EXCEPTION;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) ret = ES_VMM_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) } else if (ghcb->save.sw_exit_info_1 & 0xffffffff) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) ret = ES_VMM_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) ret = ES_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) * Boot VC Handler - This is the first VC handler during boot, there is no GHCB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) * page yet, so it only supports the MSR based communication with the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) * hypervisor and only the CPUID exit-code.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) void __init do_vc_no_ghcb(struct pt_regs *regs, unsigned long exit_code)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) unsigned int fn = lower_bits(regs->ax, 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) unsigned long val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) /* Only CPUID is supported via MSR protocol */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) if (exit_code != SVM_EXIT_CPUID)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) sev_es_wr_ghcb_msr(GHCB_CPUID_REQ(fn, GHCB_CPUID_REQ_EAX));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) VMGEXIT();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) val = sev_es_rd_ghcb_msr();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) if (GHCB_SEV_GHCB_RESP_CODE(val) != GHCB_SEV_CPUID_RESP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) regs->ax = val >> 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) sev_es_wr_ghcb_msr(GHCB_CPUID_REQ(fn, GHCB_CPUID_REQ_EBX));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) VMGEXIT();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) val = sev_es_rd_ghcb_msr();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) if (GHCB_SEV_GHCB_RESP_CODE(val) != GHCB_SEV_CPUID_RESP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) regs->bx = val >> 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) sev_es_wr_ghcb_msr(GHCB_CPUID_REQ(fn, GHCB_CPUID_REQ_ECX));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) VMGEXIT();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) val = sev_es_rd_ghcb_msr();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) if (GHCB_SEV_GHCB_RESP_CODE(val) != GHCB_SEV_CPUID_RESP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) regs->cx = val >> 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) sev_es_wr_ghcb_msr(GHCB_CPUID_REQ(fn, GHCB_CPUID_REQ_EDX));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) VMGEXIT();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) val = sev_es_rd_ghcb_msr();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) if (GHCB_SEV_GHCB_RESP_CODE(val) != GHCB_SEV_CPUID_RESP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) regs->dx = val >> 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) * This is a VC handler and the #VC is only raised when SEV-ES is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) * active, which means SEV must be active too. Do sanity checks on the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) * CPUID results to make sure the hypervisor does not trick the kernel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) * into the no-sev path. This could map sensitive data unencrypted and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) * make it accessible to the hypervisor.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) * In particular, check for:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) * - Availability of CPUID leaf 0x8000001f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) * - SEV CPUID bit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) * The hypervisor might still report the wrong C-bit position, but this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) * can't be checked here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) if (fn == 0x80000000 && (regs->ax < 0x8000001f))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) /* SEV leaf check */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) else if ((fn == 0x8000001f && !(regs->ax & BIT(1))))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) /* SEV bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) /* Skip over the CPUID two-byte opcode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) regs->ip += 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) sev_es_wr_ghcb_msr(GHCB_SEV_TERMINATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) VMGEXIT();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) /* Shouldn't get here - if we do halt the machine */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) while (true)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) asm volatile("hlt\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) static enum es_result vc_insn_string_read(struct es_em_ctxt *ctxt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) void *src, char *buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) unsigned int data_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) unsigned int count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) bool backwards)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) int i, b = backwards ? -1 : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) enum es_result ret = ES_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) for (i = 0; i < count; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) void *s = src + (i * data_size * b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) char *d = buf + (i * data_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) ret = vc_read_mem(ctxt, s, d, data_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) if (ret != ES_OK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) static enum es_result vc_insn_string_write(struct es_em_ctxt *ctxt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) void *dst, char *buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) unsigned int data_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) unsigned int count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) bool backwards)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) int i, s = backwards ? -1 : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) enum es_result ret = ES_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) for (i = 0; i < count; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) void *d = dst + (i * data_size * s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) char *b = buf + (i * data_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) ret = vc_write_mem(ctxt, d, b, data_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) if (ret != ES_OK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define IOIO_TYPE_STR BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define IOIO_TYPE_IN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define IOIO_TYPE_INS (IOIO_TYPE_IN | IOIO_TYPE_STR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define IOIO_TYPE_OUT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define IOIO_TYPE_OUTS (IOIO_TYPE_OUT | IOIO_TYPE_STR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define IOIO_REP BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define IOIO_ADDR_64 BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define IOIO_ADDR_32 BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define IOIO_ADDR_16 BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define IOIO_DATA_32 BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define IOIO_DATA_16 BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define IOIO_DATA_8 BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define IOIO_SEG_ES (0 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define IOIO_SEG_DS (3 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) static enum es_result vc_ioio_exitinfo(struct es_em_ctxt *ctxt, u64 *exitinfo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) struct insn *insn = &ctxt->insn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) *exitinfo = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) switch (insn->opcode.bytes[0]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) /* INS opcodes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) case 0x6c:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) case 0x6d:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) *exitinfo |= IOIO_TYPE_INS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) *exitinfo |= IOIO_SEG_ES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) *exitinfo |= (ctxt->regs->dx & 0xffff) << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) /* OUTS opcodes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) case 0x6e:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) case 0x6f:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) *exitinfo |= IOIO_TYPE_OUTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) *exitinfo |= IOIO_SEG_DS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) *exitinfo |= (ctxt->regs->dx & 0xffff) << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) /* IN immediate opcodes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) case 0xe4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) case 0xe5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) *exitinfo |= IOIO_TYPE_IN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) *exitinfo |= (u8)insn->immediate.value << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) /* OUT immediate opcodes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) case 0xe6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) case 0xe7:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) *exitinfo |= IOIO_TYPE_OUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) *exitinfo |= (u8)insn->immediate.value << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) /* IN register opcodes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) case 0xec:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) case 0xed:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) *exitinfo |= IOIO_TYPE_IN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) *exitinfo |= (ctxt->regs->dx & 0xffff) << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) /* OUT register opcodes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) case 0xee:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) case 0xef:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) *exitinfo |= IOIO_TYPE_OUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) *exitinfo |= (ctxt->regs->dx & 0xffff) << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) return ES_DECODE_FAILED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) switch (insn->opcode.bytes[0]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) case 0x6c:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) case 0x6e:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) case 0xe4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) case 0xe6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) case 0xec:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) case 0xee:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) /* Single byte opcodes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) *exitinfo |= IOIO_DATA_8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) /* Length determined by instruction parsing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) *exitinfo |= (insn->opnd_bytes == 2) ? IOIO_DATA_16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) : IOIO_DATA_32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) switch (insn->addr_bytes) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) *exitinfo |= IOIO_ADDR_16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) *exitinfo |= IOIO_ADDR_32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) case 8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) *exitinfo |= IOIO_ADDR_64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) if (insn_has_rep_prefix(insn))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) *exitinfo |= IOIO_REP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) return ES_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) static enum es_result vc_handle_ioio(struct ghcb *ghcb, struct es_em_ctxt *ctxt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) struct pt_regs *regs = ctxt->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) u64 exit_info_1, exit_info_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) enum es_result ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) ret = vc_ioio_exitinfo(ctxt, &exit_info_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) if (ret != ES_OK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) if (exit_info_1 & IOIO_TYPE_STR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) /* (REP) INS/OUTS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) bool df = ((regs->flags & X86_EFLAGS_DF) == X86_EFLAGS_DF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) unsigned int io_bytes, exit_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) unsigned int ghcb_count, op_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) unsigned long es_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) u64 sw_scratch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) * For the string variants with rep prefix the amount of in/out
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) * operations per #VC exception is limited so that the kernel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) * has a chance to take interrupts and re-schedule while the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) * instruction is emulated.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) io_bytes = (exit_info_1 >> 4) & 0x7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) ghcb_count = sizeof(ghcb->shared_buffer) / io_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) op_count = (exit_info_1 & IOIO_REP) ? regs->cx : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) exit_info_2 = min(op_count, ghcb_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) exit_bytes = exit_info_2 * io_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) es_base = insn_get_seg_base(ctxt->regs, INAT_SEG_REG_ES);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) /* Read bytes of OUTS into the shared buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) if (!(exit_info_1 & IOIO_TYPE_IN)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) ret = vc_insn_string_read(ctxt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) (void *)(es_base + regs->si),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) ghcb->shared_buffer, io_bytes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) exit_info_2, df);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) * Issue an VMGEXIT to the HV to consume the bytes from the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) * shared buffer or to have it write them into the shared buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) * depending on the instruction: OUTS or INS.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) sw_scratch = __pa(ghcb) + offsetof(struct ghcb, shared_buffer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) ghcb_set_sw_scratch(ghcb, sw_scratch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) ret = sev_es_ghcb_hv_call(ghcb, ctxt, SVM_EXIT_IOIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) exit_info_1, exit_info_2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) if (ret != ES_OK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) /* Read bytes from shared buffer into the guest's destination. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) if (exit_info_1 & IOIO_TYPE_IN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) ret = vc_insn_string_write(ctxt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) (void *)(es_base + regs->di),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) ghcb->shared_buffer, io_bytes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) exit_info_2, df);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) if (df)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) regs->di -= exit_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) regs->di += exit_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) if (df)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) regs->si -= exit_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) regs->si += exit_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) if (exit_info_1 & IOIO_REP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) regs->cx -= exit_info_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) ret = regs->cx ? ES_RETRY : ES_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) /* IN/OUT into/from rAX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) int bits = (exit_info_1 & 0x70) >> 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) u64 rax = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) if (!(exit_info_1 & IOIO_TYPE_IN))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) rax = lower_bits(regs->ax, bits);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) ghcb_set_rax(ghcb, rax);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) ret = sev_es_ghcb_hv_call(ghcb, ctxt, SVM_EXIT_IOIO, exit_info_1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) if (ret != ES_OK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) if (exit_info_1 & IOIO_TYPE_IN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) if (!ghcb_rax_is_valid(ghcb))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) return ES_VMM_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) regs->ax = lower_bits(ghcb->save.rax, bits);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) static enum es_result vc_handle_cpuid(struct ghcb *ghcb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) struct es_em_ctxt *ctxt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) struct pt_regs *regs = ctxt->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) u32 cr4 = native_read_cr4();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) enum es_result ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) ghcb_set_rax(ghcb, regs->ax);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) ghcb_set_rcx(ghcb, regs->cx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) if (cr4 & X86_CR4_OSXSAVE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) /* Safe to read xcr0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) ghcb_set_xcr0(ghcb, xgetbv(XCR_XFEATURE_ENABLED_MASK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) /* xgetbv will cause #GP - use reset value for xcr0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) ghcb_set_xcr0(ghcb, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) ret = sev_es_ghcb_hv_call(ghcb, ctxt, SVM_EXIT_CPUID, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) if (ret != ES_OK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) if (!(ghcb_rax_is_valid(ghcb) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) ghcb_rbx_is_valid(ghcb) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) ghcb_rcx_is_valid(ghcb) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) ghcb_rdx_is_valid(ghcb)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) return ES_VMM_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) regs->ax = ghcb->save.rax;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) regs->bx = ghcb->save.rbx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) regs->cx = ghcb->save.rcx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) regs->dx = ghcb->save.rdx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) return ES_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) static enum es_result vc_handle_rdtsc(struct ghcb *ghcb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) struct es_em_ctxt *ctxt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) unsigned long exit_code)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) bool rdtscp = (exit_code == SVM_EXIT_RDTSCP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) enum es_result ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) ret = sev_es_ghcb_hv_call(ghcb, ctxt, exit_code, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) if (ret != ES_OK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) if (!(ghcb_rax_is_valid(ghcb) && ghcb_rdx_is_valid(ghcb) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) (!rdtscp || ghcb_rcx_is_valid(ghcb))))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) return ES_VMM_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) ctxt->regs->ax = ghcb->save.rax;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) ctxt->regs->dx = ghcb->save.rdx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) if (rdtscp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) ctxt->regs->cx = ghcb->save.rcx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) return ES_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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