^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * AMD Family 10h mmconfig enablement
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/mm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/string.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/dmi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/range.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <asm/pci-direct.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/sort.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <asm/msr.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <asm/acpi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <asm/mmconfig.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <asm/pci_x86.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) struct pci_hostbridge_probe {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) u32 bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) u32 slot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) u32 vendor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) u32 device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) static u64 fam10h_pci_mmconf_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) static struct pci_hostbridge_probe pci_probes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) { 0, 0x18, PCI_VENDOR_ID_AMD, 0x1200 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) { 0xff, 0, PCI_VENDOR_ID_AMD, 0x1200 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) static int cmp_range(const void *x1, const void *x2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) const struct range *r1 = x1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) const struct range *r2 = x2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) int start1, start2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) start1 = r1->start >> 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) start2 = r2->start >> 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) return start1 - start2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define MMCONF_UNIT (1ULL << FAM10H_MMIO_CONF_BASE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define MMCONF_MASK (~(MMCONF_UNIT - 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define MMCONF_SIZE (MMCONF_UNIT << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /* need to avoid (0xfd<<32), (0xfe<<32), and (0xff<<32), ht used space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define FAM10H_PCI_MMCONF_BASE (0xfcULL<<32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define BASE_VALID(b) ((b) + MMCONF_SIZE <= (0xfdULL<<32) || (b) >= (1ULL<<40))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) static void get_fam10h_pci_mmconf_base(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) unsigned bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) unsigned slot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) int found;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) u64 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) u32 address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) u64 tom2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) u64 base = FAM10H_PCI_MMCONF_BASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) int hi_mmio_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) struct range range[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) /* only try to get setting from BSP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) if (fam10h_pci_mmconf_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) if (!early_pci_allowed())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) found = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) for (i = 0; i < ARRAY_SIZE(pci_probes); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) u32 id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) u16 device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) u16 vendor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) bus = pci_probes[i].bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) slot = pci_probes[i].slot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) id = read_pci_config(bus, slot, 0, PCI_VENDOR_ID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) vendor = id & 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) device = (id>>16) & 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) if (pci_probes[i].vendor == vendor &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) pci_probes[i].device == device) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) found = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) if (!found)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) /* SYS_CFG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) address = MSR_K8_SYSCFG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) rdmsrl(address, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) /* TOP_MEM2 is not enabled? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) if (!(val & (1<<21))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) tom2 = 1ULL << 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) /* TOP_MEM2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) address = MSR_K8_TOP_MEM2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) rdmsrl(address, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) tom2 = max(val & 0xffffff800000ULL, 1ULL << 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) if (base <= tom2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) base = (tom2 + 2 * MMCONF_UNIT - 1) & MMCONF_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) * need to check if the range is in the high mmio range that is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) * above 4G
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) hi_mmio_num = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) for (i = 0; i < 8; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) u64 start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) u64 end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) reg = read_pci_config(bus, slot, 1, 0x80 + (i << 3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) if (!(reg & 3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) start = (u64)(reg & 0xffffff00) << 8; /* 39:16 on 31:8*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) reg = read_pci_config(bus, slot, 1, 0x84 + (i << 3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) end = ((u64)(reg & 0xffffff00) << 8) | 0xffff; /* 39:16 on 31:8*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) if (end < tom2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) range[hi_mmio_num].start = start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) range[hi_mmio_num].end = end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) hi_mmio_num++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) if (!hi_mmio_num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) /* sort the range */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) sort(range, hi_mmio_num, sizeof(struct range), cmp_range, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) if (range[hi_mmio_num - 1].end < base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) if (range[0].start > base + MMCONF_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) /* need to find one window */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) base = (range[0].start & MMCONF_MASK) - MMCONF_UNIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) if ((base > tom2) && BASE_VALID(base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) base = (range[hi_mmio_num - 1].end + MMCONF_UNIT) & MMCONF_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) if (BASE_VALID(base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) /* need to find window between ranges */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) for (i = 1; i < hi_mmio_num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) base = (range[i - 1].end + MMCONF_UNIT) & MMCONF_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) val = range[i].start & MMCONF_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) if (val >= base + MMCONF_SIZE && BASE_VALID(base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) fam10h_pci_mmconf_base = base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) void fam10h_check_enable_mmcfg(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) u64 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) u32 address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) if (!(pci_probe & PCI_CHECK_ENABLE_AMD_MMCONF))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) address = MSR_FAM10H_MMIO_CONF_BASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) rdmsrl(address, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) /* try to make sure that AP's setting is identical to BSP setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) if (val & FAM10H_MMIO_CONF_ENABLE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) unsigned busnbits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) busnbits = (val >> FAM10H_MMIO_CONF_BUSRANGE_SHIFT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) FAM10H_MMIO_CONF_BUSRANGE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) /* only trust the one handle 256 buses, if acpi=off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) if (!acpi_pci_disabled || busnbits >= 8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) u64 base = val & MMCONF_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) if (!fam10h_pci_mmconf_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) fam10h_pci_mmconf_base = base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) } else if (fam10h_pci_mmconf_base == base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) * if it is not enabled, try to enable it and assume only one segment
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) * with 256 buses
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) get_fam10h_pci_mmconf_base();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) if (!fam10h_pci_mmconf_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) pci_probe &= ~PCI_CHECK_ENABLE_AMD_MMCONF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) printk(KERN_INFO "Enable MMCONFIG on AMD Family 10h\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) val &= ~((FAM10H_MMIO_CONF_BASE_MASK<<FAM10H_MMIO_CONF_BASE_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) (FAM10H_MMIO_CONF_BUSRANGE_MASK<<FAM10H_MMIO_CONF_BUSRANGE_SHIFT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) val |= fam10h_pci_mmconf_base | (8 << FAM10H_MMIO_CONF_BUSRANGE_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) FAM10H_MMIO_CONF_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) wrmsrl(address, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) static int __init set_check_enable_amd_mmconf(const struct dmi_system_id *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) pci_probe |= PCI_CHECK_ENABLE_AMD_MMCONF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) static const struct dmi_system_id __initconst mmconf_dmi_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) .callback = set_check_enable_amd_mmconf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) .ident = "Sun Microsystems Machine",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) .matches = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) DMI_MATCH(DMI_SYS_VENDOR, "Sun Microsystems"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) /* Called from a non __init function, but only on the BSP. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) void __ref check_enable_amd_mmconf_dmi(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) dmi_check_system(mmconf_dmi_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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