^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) #include <linux/linkage.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) #include <linux/signal.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #include <linux/sched.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/timex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/random.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/kprobes.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/kernel_stat.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/acpi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/pgtable.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/atomic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <asm/timer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <asm/hw_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <asm/desc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <asm/io_apic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <asm/acpi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <asm/apic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <asm/setup.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <asm/i8259.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <asm/traps.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <asm/prom.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * ISA PIC or low IO-APIC triggered (INTA-cycle or APIC) interrupts:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * (these are usually mapped to vectors 0x30-0x3f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * The IO-APIC gives us many more interrupt sources. Most of these
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * are unused but an SMP system is supposed to have enough memory ...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * sometimes (mostly wrt. hw bugs) we get corrupted vectors all
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * across the spectrum, so we really want to be prepared to get all
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * of these. Plus, more powerful systems might have more than 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * IO-APIC registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * (these are usually mapped into the 0x30-0xff vector range)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) DEFINE_PER_CPU(vector_irq_t, vector_irq) = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) [0 ... NR_VECTORS - 1] = VECTOR_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) void __init init_ISA_irqs(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) struct irq_chip *chip = legacy_pic->chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * Try to set up the through-local-APIC virtual wire mode earlier.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * On some 32-bit UP machines, whose APIC has been disabled by BIOS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * and then got re-enabled by "lapic", it hangs at boot time without this.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) init_bsp_APIC();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) legacy_pic->init(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) for (i = 0; i < nr_legacy_irqs(); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) irq_set_chip_and_handler(i, chip, handle_level_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) void __init init_IRQ(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) * On cpu 0, Assign ISA_IRQ_VECTOR(irq) to IRQ 0..15.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) * If these IRQ's are handled by legacy interrupt-controllers like PIC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) * then this configuration will likely be static after the boot. If
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) * these IRQs are handled by more modern controllers like IO-APIC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) * then this vector space can be freed and re-used dynamically as the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) * irq's migrate etc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) for (i = 0; i < nr_legacy_irqs(); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) per_cpu(vector_irq, 0)[ISA_IRQ_VECTOR(i)] = irq_to_desc(i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) BUG_ON(irq_init_percpu_irqstack(smp_processor_id()));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) x86_init.irqs.intr_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) void __init native_init_IRQ(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) /* Execute any quirks before the call gates are initialised: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) x86_init.irqs.pre_vector_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) idt_setup_apic_and_irq_gates();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) lapic_assign_system_vectors();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) if (!acpi_ioapic && !of_ioapic && nr_legacy_irqs()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) /* IRQ2 is cascade interrupt to second interrupt controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) if (request_irq(2, no_action, IRQF_NO_THREAD, "cascade", NULL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) pr_err("%s: request_irq() failed\n", "cascade");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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