Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * FPU register's regset abstraction, for ptrace, core dumps, etc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) #include <asm/fpu/internal.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) #include <asm/fpu/signal.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #include <asm/fpu/regset.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <asm/fpu/xstate.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/sched/task_stack.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  * The xstateregs_active() routine is the same as the regset_fpregs_active() routine,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13)  * as the "regset->n" for the xstate regset will be updated based on the feature
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14)  * capabilities supported by the xsave.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) int regset_fpregs_active(struct task_struct *target, const struct user_regset *regset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 	return regset->n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) int regset_xregset_fpregs_active(struct task_struct *target, const struct user_regset *regset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 	if (boot_cpu_has(X86_FEATURE_FXSR))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 		return regset->n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) int xfpregs_get(struct task_struct *target, const struct user_regset *regset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 		struct membuf to)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 	struct fpu *fpu = &target->thread.fpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	if (!boot_cpu_has(X86_FEATURE_FXSR))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	fpu__prepare_read(fpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	fpstate_sanitize_xstate(fpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	return membuf_write(&to, &fpu->state.fxsave, sizeof(struct fxregs_state));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) int xfpregs_set(struct task_struct *target, const struct user_regset *regset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 		unsigned int pos, unsigned int count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 		const void *kbuf, const void __user *ubuf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	struct fpu *fpu = &target->thread.fpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	if (!boot_cpu_has(X86_FEATURE_FXSR))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	fpu__prepare_write(fpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	fpstate_sanitize_xstate(fpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 				 &fpu->state.fxsave, 0, -1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	 * mxcsr reserved bits must be masked to zero for security reasons.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	fpu->state.fxsave.mxcsr &= mxcsr_feature_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	 * update the header bits in the xsave header, indicating the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	 * presence of FP and SSE state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	if (boot_cpu_has(X86_FEATURE_XSAVE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 		fpu->state.xsave.header.xfeatures |= XFEATURE_MASK_FPSSE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) int xstateregs_get(struct task_struct *target, const struct user_regset *regset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 		struct membuf to)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	struct fpu *fpu = &target->thread.fpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	struct xregs_state *xsave;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	if (!boot_cpu_has(X86_FEATURE_XSAVE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	xsave = &fpu->state.xsave;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	fpu__prepare_read(fpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	if (using_compacted_format()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 		copy_xstate_to_kernel(to, xsave);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 		fpstate_sanitize_xstate(fpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 		 * Copy the 48 bytes defined by the software into the xsave
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 		 * area in the thread struct, so that we can copy the whole
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 		 * area to user using one user_regset_copyout().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 		memcpy(&xsave->i387.sw_reserved, xstate_fx_sw_bytes, sizeof(xstate_fx_sw_bytes));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 		 * Copy the xstate memory layout.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 		return membuf_write(&to, xsave, fpu_user_xstate_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) int xstateregs_set(struct task_struct *target, const struct user_regset *regset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 		  unsigned int pos, unsigned int count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 		  const void *kbuf, const void __user *ubuf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	struct fpu *fpu = &target->thread.fpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	struct xregs_state *xsave;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	if (!boot_cpu_has(X86_FEATURE_XSAVE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	 * A whole standard-format XSAVE buffer is needed:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	if (pos != 0 || count != fpu_user_xstate_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 		return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	xsave = &fpu->state.xsave;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	fpu__prepare_write(fpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	if (using_compacted_format()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 		if (kbuf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 			ret = copy_kernel_to_xstate(xsave, kbuf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 		else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 			ret = copy_user_to_xstate(xsave, ubuf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 		ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, xsave, 0, -1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 		if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 			ret = validate_user_xstate_header(&xsave->header);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	 * mxcsr reserved bits must be masked to zero for security reasons.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	xsave->i387.mxcsr &= mxcsr_feature_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	 * In case of failure, mark all states as init:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 		fpstate_init(&fpu->state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #if defined CONFIG_X86_32 || defined CONFIG_IA32_EMULATION
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)  * FPU tag word conversions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) static inline unsigned short twd_i387_to_fxsr(unsigned short twd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	unsigned int tmp; /* to avoid 16 bit prefixes in the code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	/* Transform each pair of bits into 01 (valid) or 00 (empty) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	tmp = ~twd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	tmp = (tmp | (tmp>>1)) & 0x5555; /* 0V0V0V0V0V0V0V0V */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	/* and move the valid bits to the lower byte. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	tmp = (tmp | (tmp >> 1)) & 0x3333; /* 00VV00VV00VV00VV */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	tmp = (tmp | (tmp >> 2)) & 0x0f0f; /* 0000VVVV0000VVVV */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	tmp = (tmp | (tmp >> 4)) & 0x00ff; /* 00000000VVVVVVVV */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	return tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define FPREG_ADDR(f, n)	((void *)&(f)->st_space + (n) * 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define FP_EXP_TAG_VALID	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define FP_EXP_TAG_ZERO		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define FP_EXP_TAG_SPECIAL	2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define FP_EXP_TAG_EMPTY	3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) static inline u32 twd_fxsr_to_i387(struct fxregs_state *fxsave)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	struct _fpxreg *st;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	u32 tos = (fxsave->swd >> 11) & 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	u32 twd = (unsigned long) fxsave->twd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	u32 tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	u32 ret = 0xffff0000u;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	for (i = 0; i < 8; i++, twd >>= 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 		if (twd & 0x1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 			st = FPREG_ADDR(fxsave, (i - tos) & 7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 			switch (st->exponent & 0x7fff) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 			case 0x7fff:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 				tag = FP_EXP_TAG_SPECIAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 				break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 			case 0x0000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 				if (!st->significand[0] &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 				    !st->significand[1] &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 				    !st->significand[2] &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 				    !st->significand[3])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 					tag = FP_EXP_TAG_ZERO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 				else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 					tag = FP_EXP_TAG_SPECIAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 				break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 			default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 				if (st->significand[3] & 0x8000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 					tag = FP_EXP_TAG_VALID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 				else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 					tag = FP_EXP_TAG_SPECIAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 				break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 			}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 		} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 			tag = FP_EXP_TAG_EMPTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 		ret |= tag << (2 * i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)  * FXSR floating point environment conversions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) convert_from_fxsr(struct user_i387_ia32_struct *env, struct task_struct *tsk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	struct fxregs_state *fxsave = &tsk->thread.fpu.state.fxsave;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	struct _fpreg *to = (struct _fpreg *) &env->st_space[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	struct _fpxreg *from = (struct _fpxreg *) &fxsave->st_space[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	env->cwd = fxsave->cwd | 0xffff0000u;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	env->swd = fxsave->swd | 0xffff0000u;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	env->twd = twd_fxsr_to_i387(fxsave);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #ifdef CONFIG_X86_64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	env->fip = fxsave->rip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	env->foo = fxsave->rdp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	 * should be actually ds/cs at fpu exception time, but
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	 * that information is not available in 64bit mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	env->fcs = task_pt_regs(tsk)->cs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	if (tsk == current) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 		savesegment(ds, env->fos);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 		env->fos = tsk->thread.ds;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	env->fos |= 0xffff0000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	env->fip = fxsave->fip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	env->fcs = (u16) fxsave->fcs | ((u32) fxsave->fop << 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	env->foo = fxsave->foo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	env->fos = fxsave->fos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	for (i = 0; i < 8; ++i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 		memcpy(&to[i], &from[i], sizeof(to[0]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) void convert_to_fxsr(struct fxregs_state *fxsave,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 		     const struct user_i387_ia32_struct *env)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	struct _fpreg *from = (struct _fpreg *) &env->st_space[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	struct _fpxreg *to = (struct _fpxreg *) &fxsave->st_space[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	fxsave->cwd = env->cwd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	fxsave->swd = env->swd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	fxsave->twd = twd_i387_to_fxsr(env->twd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	fxsave->fop = (u16) ((u32) env->fcs >> 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #ifdef CONFIG_X86_64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	fxsave->rip = env->fip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	fxsave->rdp = env->foo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	/* cs and ds ignored */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	fxsave->fip = env->fip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	fxsave->fcs = (env->fcs & 0xffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	fxsave->foo = env->foo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	fxsave->fos = env->fos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	for (i = 0; i < 8; ++i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 		memcpy(&to[i], &from[i], sizeof(from[0]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) int fpregs_get(struct task_struct *target, const struct user_regset *regset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	       struct membuf to)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	struct fpu *fpu = &target->thread.fpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	struct user_i387_ia32_struct env;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	fpu__prepare_read(fpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	if (!boot_cpu_has(X86_FEATURE_FPU))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 		return fpregs_soft_get(target, regset, to);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	if (!boot_cpu_has(X86_FEATURE_FXSR)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 		return membuf_write(&to, &fpu->state.fsave,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 				    sizeof(struct fregs_state));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	fpstate_sanitize_xstate(fpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	if (to.left == sizeof(env)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 		convert_from_fxsr(to.p, target);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	convert_from_fxsr(&env, target);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	return membuf_write(&to, &env, sizeof(env));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) int fpregs_set(struct task_struct *target, const struct user_regset *regset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	       unsigned int pos, unsigned int count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	       const void *kbuf, const void __user *ubuf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	struct fpu *fpu = &target->thread.fpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	struct user_i387_ia32_struct env;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 	fpu__prepare_write(fpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	fpstate_sanitize_xstate(fpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	if (!boot_cpu_has(X86_FEATURE_FPU))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 		return fpregs_soft_set(target, regset, pos, count, kbuf, ubuf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	if (!boot_cpu_has(X86_FEATURE_FXSR))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 		return user_regset_copyin(&pos, &count, &kbuf, &ubuf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 					  &fpu->state.fsave, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 					  -1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 	if (pos > 0 || count < sizeof(env))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 		convert_from_fxsr(&env, target);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 	ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &env, 0, -1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 	if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 		convert_to_fxsr(&target->thread.fpu.state.fxsave, &env);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 	 * update the header bit in the xsave header, indicating the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 	 * presence of FP.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 	if (boot_cpu_has(X86_FEATURE_XSAVE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 		fpu->state.xsave.header.xfeatures |= XFEATURE_MASK_FP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) #endif	/* CONFIG_X86_32 || CONFIG_IA32_EMULATION */