^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) #include <linux/console.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #include <linux/string.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/screen_info.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/usb/ch9.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/pci_regs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/pci_ids.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/pgtable.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <asm/processor.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <asm/fcntl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <asm/setup.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <xen/hvc-console.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <asm/pci-direct.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <asm/fixmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/usb/ehci_def.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/usb/xhci-dbgp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <asm/pci_x86.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) /* Simple VGA output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define VGABASE (__ISA_IO_base + 0xb8000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) static int max_ypos = 25, max_xpos = 80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) static int current_ypos = 25, current_xpos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) static void early_vga_write(struct console *con, const char *str, unsigned n)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) char c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) int i, k, j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) while ((c = *str++) != '\0' && n-- > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) if (current_ypos >= max_ypos) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) /* scroll 1 line up */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) for (k = 1, j = 0; k < max_ypos; k++, j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) for (i = 0; i < max_xpos; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) writew(readw(VGABASE+2*(max_xpos*k+i)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) VGABASE + 2*(max_xpos*j + i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) for (i = 0; i < max_xpos; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) writew(0x720, VGABASE + 2*(max_xpos*j + i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) current_ypos = max_ypos-1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #ifdef CONFIG_KGDB_KDB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) if (c == '\b') {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) if (current_xpos > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) current_xpos--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) } else if (c == '\r') {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) current_xpos = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) if (c == '\n') {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) current_xpos = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) current_ypos++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) } else if (c != '\r') {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) writew(((0x7 << 8) | (unsigned short) c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) VGABASE + 2*(max_xpos*current_ypos +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) current_xpos++));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) if (current_xpos >= max_xpos) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) current_xpos = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) current_ypos++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) static struct console early_vga_console = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) .name = "earlyvga",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) .write = early_vga_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) .flags = CON_PRINTBUFFER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) .index = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) /* Serial functions loosely based on a similar package from Klaus P. Gerlicher */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) static unsigned long early_serial_base = 0x3f8; /* ttyS0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define XMTRDY 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define DLAB 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define TXR 0 /* Transmit register (WRITE) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define RXR 0 /* Receive register (READ) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define IER 1 /* Interrupt Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define IIR 2 /* Interrupt ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define FCR 2 /* FIFO control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define LCR 3 /* Line control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define MCR 4 /* Modem control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define LSR 5 /* Line Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define MSR 6 /* Modem Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define DLL 0 /* Divisor Latch Low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define DLH 1 /* Divisor latch High */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) static unsigned int io_serial_in(unsigned long addr, int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) return inb(addr + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) static void io_serial_out(unsigned long addr, int offset, int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) outb(value, addr + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) static unsigned int (*serial_in)(unsigned long addr, int offset) = io_serial_in;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) static void (*serial_out)(unsigned long addr, int offset, int value) = io_serial_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) static int early_serial_putc(unsigned char ch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) unsigned timeout = 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) while ((serial_in(early_serial_base, LSR) & XMTRDY) == 0 && --timeout)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) serial_out(early_serial_base, TXR, ch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) return timeout ? 0 : -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) static void early_serial_write(struct console *con, const char *s, unsigned n)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) while (*s && n-- > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) if (*s == '\n')
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) early_serial_putc('\r');
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) early_serial_putc(*s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) s++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) static __init void early_serial_hw_init(unsigned divisor)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) unsigned char c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) serial_out(early_serial_base, LCR, 0x3); /* 8n1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) serial_out(early_serial_base, IER, 0); /* no interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) serial_out(early_serial_base, FCR, 0); /* no fifo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) serial_out(early_serial_base, MCR, 0x3); /* DTR + RTS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) c = serial_in(early_serial_base, LCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) serial_out(early_serial_base, LCR, c | DLAB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) serial_out(early_serial_base, DLL, divisor & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) serial_out(early_serial_base, DLH, (divisor >> 8) & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) serial_out(early_serial_base, LCR, c & ~DLAB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define DEFAULT_BAUD 9600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) static __init void early_serial_init(char *s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) unsigned divisor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) unsigned long baud = DEFAULT_BAUD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) char *e;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) if (*s == ',')
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) ++s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) if (*s) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) unsigned port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) if (!strncmp(s, "0x", 2)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) early_serial_base = simple_strtoul(s, &e, 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) static const int __initconst bases[] = { 0x3f8, 0x2f8 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) if (!strncmp(s, "ttyS", 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) s += 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) port = simple_strtoul(s, &e, 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) if (port > 1 || s == e)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) port = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) early_serial_base = bases[port];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) s += strcspn(s, ",");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) if (*s == ',')
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) s++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) if (*s) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) baud = simple_strtoull(s, &e, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) if (baud == 0 || s == e)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) baud = DEFAULT_BAUD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) /* Convert from baud to divisor value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) divisor = 115200 / baud;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) /* These will always be IO based ports */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) serial_in = io_serial_in;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) serial_out = io_serial_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) /* Set up the HW */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) early_serial_hw_init(divisor);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #ifdef CONFIG_PCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) static void mem32_serial_out(unsigned long addr, int offset, int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) u32 __iomem *vaddr = (u32 __iomem *)addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) /* shift implied by pointer type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) writel(value, vaddr + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) static unsigned int mem32_serial_in(unsigned long addr, int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) u32 __iomem *vaddr = (u32 __iomem *)addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) /* shift implied by pointer type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) return readl(vaddr + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) * early_pci_serial_init()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) * This function is invoked when the early_printk param starts with "pciserial"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) * The rest of the param should be "[force],B:D.F,baud", where B, D & F describe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) * the location of a PCI device that must be a UART device. "force" is optional
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) * and overrides the use of an UART device with a wrong PCI class code.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) static __init void early_pci_serial_init(char *s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) unsigned divisor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) unsigned long baud = DEFAULT_BAUD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) u8 bus, slot, func;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) u32 classcode, bar0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) u16 cmdreg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) char *e;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) int force = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) if (*s == ',')
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) ++s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) if (*s == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) /* Force the use of an UART device with wrong class code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) if (!strncmp(s, "force,", 6)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) force = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) s += 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) * Part the param to get the BDF values
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) bus = (u8)simple_strtoul(s, &e, 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) s = e;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) if (*s != ':')
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) ++s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) slot = (u8)simple_strtoul(s, &e, 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) s = e;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) if (*s != '.')
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) ++s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) func = (u8)simple_strtoul(s, &e, 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) s = e;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) /* A baud might be following */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) if (*s == ',')
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) s++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) * Find the device from the BDF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) cmdreg = read_pci_config(bus, slot, func, PCI_COMMAND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) classcode = read_pci_config(bus, slot, func, PCI_CLASS_REVISION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) bar0 = read_pci_config(bus, slot, func, PCI_BASE_ADDRESS_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) * Verify it is a UART type device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) if (((classcode >> 16 != PCI_CLASS_COMMUNICATION_MODEM) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) (classcode >> 16 != PCI_CLASS_COMMUNICATION_SERIAL)) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) (((classcode >> 8) & 0xff) != 0x02)) /* 16550 I/F at BAR0 */ {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) if (!force)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) * Determine if it is IO or memory mapped
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) if (bar0 & 0x01) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) /* it is IO mapped */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) serial_in = io_serial_in;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) serial_out = io_serial_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) early_serial_base = bar0&0xfffffffc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) write_pci_config(bus, slot, func, PCI_COMMAND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) cmdreg|PCI_COMMAND_IO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) /* It is memory mapped - assume 32-bit alignment */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) serial_in = mem32_serial_in;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) serial_out = mem32_serial_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) /* WARNING! assuming the address is always in the first 4G */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) early_serial_base =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) (unsigned long)early_ioremap(bar0 & 0xfffffff0, 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) write_pci_config(bus, slot, func, PCI_COMMAND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) cmdreg|PCI_COMMAND_MEMORY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) * Initialize the hardware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) if (*s) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) if (strcmp(s, "nocfg") == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) /* Sometimes, we want to leave the UART alone
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) * and assume the BIOS has set it up correctly.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) * "nocfg" tells us this is the case, and we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) * should do no more setup.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) if (kstrtoul(s, 0, &baud) < 0 || baud == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) baud = DEFAULT_BAUD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) /* Convert from baud to divisor value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) divisor = 115200 / baud;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) /* Set up the HW */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) early_serial_hw_init(divisor);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) static struct console early_serial_console = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) .name = "earlyser",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) .write = early_serial_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) .flags = CON_PRINTBUFFER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) .index = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) static void early_console_register(struct console *con, int keep_early)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) if (con->index != -1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) printk(KERN_CRIT "ERROR: earlyprintk= %s already used\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) con->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) early_console = con;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) if (keep_early)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) early_console->flags &= ~CON_BOOT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) early_console->flags |= CON_BOOT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) register_console(early_console);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) static int __init setup_early_printk(char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) int keep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) if (!buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) if (early_console)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) keep = (strstr(buf, "keep") != NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) while (*buf != '\0') {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) if (!strncmp(buf, "serial", 6)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) buf += 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) early_serial_init(buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) early_console_register(&early_serial_console, keep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) if (!strncmp(buf, ",ttyS", 5))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) buf += 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) if (!strncmp(buf, "ttyS", 4)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) early_serial_init(buf + 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) early_console_register(&early_serial_console, keep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) #ifdef CONFIG_PCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) if (!strncmp(buf, "pciserial", 9)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) early_pci_serial_init(buf + 9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) early_console_register(&early_serial_console, keep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) buf += 9; /* Keep from match the above "serial" */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) if (!strncmp(buf, "vga", 3) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) boot_params.screen_info.orig_video_isVGA == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) max_xpos = boot_params.screen_info.orig_video_cols;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) max_ypos = boot_params.screen_info.orig_video_lines;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) current_ypos = boot_params.screen_info.orig_y;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) early_console_register(&early_vga_console, keep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) #ifdef CONFIG_EARLY_PRINTK_DBGP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) if (!strncmp(buf, "dbgp", 4) && !early_dbgp_init(buf + 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) early_console_register(&early_dbgp_console, keep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) #ifdef CONFIG_HVC_XEN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) if (!strncmp(buf, "xen", 3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) early_console_register(&xenboot_console, keep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) #ifdef CONFIG_EARLY_PRINTK_USB_XDBC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) if (!strncmp(buf, "xdbc", 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) early_xdbc_parse_parameter(buf + 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) buf++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) early_param("earlyprintk", setup_early_printk);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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