^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /* Various workarounds for chipset bugs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) This code runs very early and can't use the regular PCI subsystem
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) The entries are keyed to PCI bridges which usually identify chipsets
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) uniquely.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) This is only for whole classes of chipsets with specific problems which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) need early invasive action (e.g. before the timers are initialized).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) Most PCI device specific workarounds can be done later and should be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) in standard PCI quirks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) Mainboard specific bugs should be handled by DMI entries.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) CPU specific bugs in setup.c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/acpi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/pci_ids.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/bcma/bcma.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/bcma/bcma_regs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/platform_data/x86/apple.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <drm/i915_drm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <asm/pci-direct.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <asm/dma.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <asm/io_apic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <asm/apic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <asm/hpet.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <asm/iommu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <asm/gart.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <asm/irq_remapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <asm/early_ioremap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) static void __init fix_hypertransport_config(int num, int slot, int func)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) u32 htcfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * we found a hypertransport bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * make sure that we are broadcasting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * interrupts to all cpus on the ht bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * if we're using extended apic ids
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) htcfg = read_pci_config(num, slot, func, 0x68);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) if (htcfg & (1 << 18)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) printk(KERN_INFO "Detected use of extended apic ids "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) "on hypertransport bus\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) if ((htcfg & (1 << 17)) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) printk(KERN_INFO "Enabling hypertransport extended "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) "apic interrupt broadcast\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) printk(KERN_INFO "Note this is a bios bug, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) "please contact your hw vendor\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) htcfg |= (1 << 17);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) write_pci_config(num, slot, func, 0x68, htcfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) static void __init via_bugs(int num, int slot, int func)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #ifdef CONFIG_GART_IOMMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) if ((max_pfn > MAX_DMA32_PFN || force_iommu) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) !gart_iommu_aperture_allowed) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) printk(KERN_INFO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) "Looks like a VIA chipset. Disabling IOMMU."
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) " Override with iommu=allowed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) gart_iommu_aperture_disabled = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #ifdef CONFIG_ACPI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #ifdef CONFIG_X86_IO_APIC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) static int __init nvidia_hpet_check(struct acpi_table_header *header)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #endif /* CONFIG_X86_IO_APIC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #endif /* CONFIG_ACPI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) static void __init nvidia_bugs(int num, int slot, int func)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #ifdef CONFIG_ACPI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #ifdef CONFIG_X86_IO_APIC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) * Only applies to Nvidia root ports (bus 0) and not to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) * Nvidia graphics cards with PCI ports on secondary buses.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) if (num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) * All timer overrides on Nvidia are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) * wrong unless HPET is enabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) * Unfortunately that's not true on many Asus boards.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) * We don't know yet how to detect this automatically, but
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) * at least allow a command line override.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) if (acpi_use_timer_override)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) if (acpi_table_parse(ACPI_SIG_HPET, nvidia_hpet_check)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) acpi_skip_timer_override = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) printk(KERN_INFO "Nvidia board "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) "detected. Ignoring ACPI "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) "timer override.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) printk(KERN_INFO "If you got timer trouble "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) "try acpi_use_timer_override\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) /* RED-PEN skip them on mptables too? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #if defined(CONFIG_ACPI) && defined(CONFIG_X86_IO_APIC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) static u32 __init ati_ixp4x0_rev(int num, int slot, int func)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) u32 d;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) u8 b;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) b = read_pci_config_byte(num, slot, func, 0xac);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) b &= ~(1<<5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) write_pci_config_byte(num, slot, func, 0xac, b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) d = read_pci_config(num, slot, func, 0x70);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) d |= 1<<8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) write_pci_config(num, slot, func, 0x70, d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) d = read_pci_config(num, slot, func, 0x8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) d &= 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) return d;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) static void __init ati_bugs(int num, int slot, int func)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) u32 d;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) u8 b;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) if (acpi_use_timer_override)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) d = ati_ixp4x0_rev(num, slot, func);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) if (d < 0x82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) acpi_skip_timer_override = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) /* check for IRQ0 interrupt swap */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) outb(0x72, 0xcd6); b = inb(0xcd7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) if (!(b & 0x2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) acpi_skip_timer_override = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) if (acpi_skip_timer_override) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) printk(KERN_INFO "SB4X0 revision 0x%x\n", d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) printk(KERN_INFO "Ignoring ACPI timer override.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) printk(KERN_INFO "If you got timer trouble "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) "try acpi_use_timer_override\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) static u32 __init ati_sbx00_rev(int num, int slot, int func)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) u32 d;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) d = read_pci_config(num, slot, func, 0x8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) d &= 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) return d;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) static void __init ati_bugs_contd(int num, int slot, int func)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) u32 d, rev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) rev = ati_sbx00_rev(num, slot, func);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) if (rev >= 0x40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) acpi_fix_pin2_polarity = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) * SB600: revisions 0x11, 0x12, 0x13, 0x14, ...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) * SB700: revisions 0x39, 0x3a, ...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) * SB800: revisions 0x40, 0x41, ...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) if (rev >= 0x39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) if (acpi_use_timer_override)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) /* check for IRQ0 interrupt swap */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) d = read_pci_config(num, slot, func, 0x64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) if (!(d & (1<<14)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) acpi_skip_timer_override = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) if (acpi_skip_timer_override) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) printk(KERN_INFO "SB600 revision 0x%x\n", rev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) printk(KERN_INFO "Ignoring ACPI timer override.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) printk(KERN_INFO "If you got timer trouble "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) "try acpi_use_timer_override\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) static void __init ati_bugs(int num, int slot, int func)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) static void __init ati_bugs_contd(int num, int slot, int func)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) static void __init intel_remapping_check(int num, int slot, int func)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) u8 revision;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) u16 device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) device = read_pci_config_16(num, slot, func, PCI_DEVICE_ID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) revision = read_pci_config_byte(num, slot, func, PCI_REVISION_ID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) * Revision <= 13 of all triggering devices id in this quirk
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) * have a problem draining interrupts when irq remapping is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) * enabled, and should be flagged as broken. Additionally
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) * revision 0x22 of device id 0x3405 has this problem.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) if (revision <= 0x13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) set_irq_remapping_broken();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) else if (device == 0x3405 && revision == 0x22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) set_irq_remapping_broken();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) * Systems with Intel graphics controllers set aside memory exclusively
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) * for gfx driver use. This memory is not marked in the E820 as reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) * or as RAM, and so is subject to overlap from E820 manipulation later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) * in the boot process. On some systems, MMIO space is allocated on top,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) * despite the efforts of the "RAM buffer" approach, which simply rounds
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) * memory boundaries up to 64M to try to catch space that may decode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) * as RAM and so is not suitable for MMIO.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define KB(x) ((x) * 1024UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define MB(x) (KB (KB (x)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) static resource_size_t __init i830_tseg_size(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) u8 esmramc = read_pci_config_byte(0, 0, 0, I830_ESMRAMC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) if (!(esmramc & TSEG_ENABLE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) if (esmramc & I830_TSEG_SIZE_1M)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) return MB(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) return KB(512);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) static resource_size_t __init i845_tseg_size(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) u8 esmramc = read_pci_config_byte(0, 0, 0, I845_ESMRAMC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) u8 tseg_size = esmramc & I845_TSEG_SIZE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) if (!(esmramc & TSEG_ENABLE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) switch (tseg_size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) case I845_TSEG_SIZE_512K: return KB(512);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) case I845_TSEG_SIZE_1M: return MB(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) WARN(1, "Unknown ESMRAMC value: %x!\n", esmramc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) static resource_size_t __init i85x_tseg_size(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) u8 esmramc = read_pci_config_byte(0, 0, 0, I85X_ESMRAMC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) if (!(esmramc & TSEG_ENABLE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) return MB(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) static resource_size_t __init i830_mem_size(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) return read_pci_config_byte(0, 0, 0, I830_DRB3) * MB(32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) static resource_size_t __init i85x_mem_size(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) return read_pci_config_byte(0, 0, 1, I85X_DRB3) * MB(32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) * On 830/845/85x the stolen memory base isn't available in any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) * register. We need to calculate it as TOM-TSEG_SIZE-stolen_size.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) static resource_size_t __init i830_stolen_base(int num, int slot, int func,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) resource_size_t stolen_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) return i830_mem_size() - i830_tseg_size() - stolen_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) static resource_size_t __init i845_stolen_base(int num, int slot, int func,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) resource_size_t stolen_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) return i830_mem_size() - i845_tseg_size() - stolen_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) static resource_size_t __init i85x_stolen_base(int num, int slot, int func,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) resource_size_t stolen_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) return i85x_mem_size() - i85x_tseg_size() - stolen_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) static resource_size_t __init i865_stolen_base(int num, int slot, int func,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) resource_size_t stolen_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) u16 toud = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) toud = read_pci_config_16(0, 0, 0, I865_TOUD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) return toud * KB(64) + i845_tseg_size();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) static resource_size_t __init gen3_stolen_base(int num, int slot, int func,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) resource_size_t stolen_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) u32 bsm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) /* Almost universally we can find the Graphics Base of Stolen Memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) * at register BSM (0x5c) in the igfx configuration space. On a few
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) * (desktop) machines this is also mirrored in the bridge device at
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) * different locations, or in the MCHBAR.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) bsm = read_pci_config(num, slot, func, INTEL_BSM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) return bsm & INTEL_BSM_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) static resource_size_t __init gen11_stolen_base(int num, int slot, int func,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) resource_size_t stolen_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) u64 bsm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) bsm = read_pci_config(num, slot, func, INTEL_GEN11_BSM_DW0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) bsm &= INTEL_BSM_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) bsm |= (u64)read_pci_config(num, slot, func, INTEL_GEN11_BSM_DW1) << 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) return bsm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) static resource_size_t __init i830_stolen_size(int num, int slot, int func)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) u16 gmch_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) u16 gms;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) gmch_ctrl = read_pci_config_16(0, 0, 0, I830_GMCH_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) gms = gmch_ctrl & I830_GMCH_GMS_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) switch (gms) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) case I830_GMCH_GMS_STOLEN_512: return KB(512);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) case I830_GMCH_GMS_STOLEN_1024: return MB(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) case I830_GMCH_GMS_STOLEN_8192: return MB(8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) /* local memory isn't part of the normal address space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) case I830_GMCH_GMS_LOCAL: return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) WARN(1, "Unknown GMCH_CTRL value: %x!\n", gmch_ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) static resource_size_t __init gen3_stolen_size(int num, int slot, int func)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) u16 gmch_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) u16 gms;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) gmch_ctrl = read_pci_config_16(0, 0, 0, I830_GMCH_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) gms = gmch_ctrl & I855_GMCH_GMS_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) switch (gms) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) case I855_GMCH_GMS_STOLEN_1M: return MB(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) case I855_GMCH_GMS_STOLEN_4M: return MB(4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) case I855_GMCH_GMS_STOLEN_8M: return MB(8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) case I855_GMCH_GMS_STOLEN_16M: return MB(16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) case I855_GMCH_GMS_STOLEN_32M: return MB(32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) case I915_GMCH_GMS_STOLEN_48M: return MB(48);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) case I915_GMCH_GMS_STOLEN_64M: return MB(64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) case G33_GMCH_GMS_STOLEN_128M: return MB(128);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) case G33_GMCH_GMS_STOLEN_256M: return MB(256);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) case INTEL_GMCH_GMS_STOLEN_96M: return MB(96);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) case INTEL_GMCH_GMS_STOLEN_160M:return MB(160);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) case INTEL_GMCH_GMS_STOLEN_224M:return MB(224);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) case INTEL_GMCH_GMS_STOLEN_352M:return MB(352);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) WARN(1, "Unknown GMCH_CTRL value: %x!\n", gmch_ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) static resource_size_t __init gen6_stolen_size(int num, int slot, int func)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) u16 gmch_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) u16 gms;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) gmch_ctrl = read_pci_config_16(num, slot, func, SNB_GMCH_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) gms = (gmch_ctrl >> SNB_GMCH_GMS_SHIFT) & SNB_GMCH_GMS_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) return gms * MB(32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) static resource_size_t __init gen8_stolen_size(int num, int slot, int func)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) u16 gmch_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) u16 gms;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) gmch_ctrl = read_pci_config_16(num, slot, func, SNB_GMCH_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) gms = (gmch_ctrl >> BDW_GMCH_GMS_SHIFT) & BDW_GMCH_GMS_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) return gms * MB(32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) static resource_size_t __init chv_stolen_size(int num, int slot, int func)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) u16 gmch_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) u16 gms;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) gmch_ctrl = read_pci_config_16(num, slot, func, SNB_GMCH_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) gms = (gmch_ctrl >> SNB_GMCH_GMS_SHIFT) & SNB_GMCH_GMS_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) * 0x0 to 0x10: 32MB increments starting at 0MB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) * 0x11 to 0x16: 4MB increments starting at 8MB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) * 0x17 to 0x1d: 4MB increments start at 36MB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) if (gms < 0x11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) return gms * MB(32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) else if (gms < 0x17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) return (gms - 0x11) * MB(4) + MB(8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) return (gms - 0x17) * MB(4) + MB(36);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) static resource_size_t __init gen9_stolen_size(int num, int slot, int func)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) u16 gmch_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) u16 gms;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) gmch_ctrl = read_pci_config_16(num, slot, func, SNB_GMCH_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) gms = (gmch_ctrl >> BDW_GMCH_GMS_SHIFT) & BDW_GMCH_GMS_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) /* 0x0 to 0xef: 32MB increments starting at 0MB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) /* 0xf0 to 0xfe: 4MB increments starting at 4MB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) if (gms < 0xf0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) return gms * MB(32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) return (gms - 0xf0) * MB(4) + MB(4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) struct intel_early_ops {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) resource_size_t (*stolen_size)(int num, int slot, int func);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) resource_size_t (*stolen_base)(int num, int slot, int func,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) resource_size_t size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) static const struct intel_early_ops i830_early_ops __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) .stolen_base = i830_stolen_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) .stolen_size = i830_stolen_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) static const struct intel_early_ops i845_early_ops __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) .stolen_base = i845_stolen_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) .stolen_size = i830_stolen_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) static const struct intel_early_ops i85x_early_ops __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) .stolen_base = i85x_stolen_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) .stolen_size = gen3_stolen_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) static const struct intel_early_ops i865_early_ops __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) .stolen_base = i865_stolen_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) .stolen_size = gen3_stolen_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) static const struct intel_early_ops gen3_early_ops __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) .stolen_base = gen3_stolen_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) .stolen_size = gen3_stolen_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) static const struct intel_early_ops gen6_early_ops __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) .stolen_base = gen3_stolen_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) .stolen_size = gen6_stolen_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) static const struct intel_early_ops gen8_early_ops __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) .stolen_base = gen3_stolen_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) .stolen_size = gen8_stolen_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) static const struct intel_early_ops gen9_early_ops __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) .stolen_base = gen3_stolen_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) .stolen_size = gen9_stolen_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) static const struct intel_early_ops chv_early_ops __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) .stolen_base = gen3_stolen_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) .stolen_size = chv_stolen_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) static const struct intel_early_ops gen11_early_ops __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) .stolen_base = gen11_stolen_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) .stolen_size = gen9_stolen_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) /* Intel integrated GPUs for which we need to reserve "stolen memory" */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) static const struct pci_device_id intel_early_ids[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) INTEL_I830_IDS(&i830_early_ops),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) INTEL_I845G_IDS(&i845_early_ops),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) INTEL_I85X_IDS(&i85x_early_ops),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) INTEL_I865G_IDS(&i865_early_ops),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) INTEL_I915G_IDS(&gen3_early_ops),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) INTEL_I915GM_IDS(&gen3_early_ops),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) INTEL_I945G_IDS(&gen3_early_ops),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) INTEL_I945GM_IDS(&gen3_early_ops),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) INTEL_VLV_IDS(&gen6_early_ops),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) INTEL_PINEVIEW_G_IDS(&gen3_early_ops),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) INTEL_PINEVIEW_M_IDS(&gen3_early_ops),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) INTEL_I965G_IDS(&gen3_early_ops),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) INTEL_G33_IDS(&gen3_early_ops),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) INTEL_I965GM_IDS(&gen3_early_ops),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) INTEL_GM45_IDS(&gen3_early_ops),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) INTEL_G45_IDS(&gen3_early_ops),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) INTEL_IRONLAKE_D_IDS(&gen3_early_ops),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) INTEL_IRONLAKE_M_IDS(&gen3_early_ops),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) INTEL_SNB_D_IDS(&gen6_early_ops),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) INTEL_SNB_M_IDS(&gen6_early_ops),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) INTEL_IVB_M_IDS(&gen6_early_ops),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) INTEL_IVB_D_IDS(&gen6_early_ops),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) INTEL_HSW_IDS(&gen6_early_ops),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) INTEL_BDW_IDS(&gen8_early_ops),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) INTEL_CHV_IDS(&chv_early_ops),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) INTEL_SKL_IDS(&gen9_early_ops),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) INTEL_BXT_IDS(&gen9_early_ops),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) INTEL_KBL_IDS(&gen9_early_ops),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) INTEL_CFL_IDS(&gen9_early_ops),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) INTEL_GLK_IDS(&gen9_early_ops),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) INTEL_CNL_IDS(&gen9_early_ops),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) INTEL_ICL_11_IDS(&gen11_early_ops),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) INTEL_EHL_IDS(&gen11_early_ops),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) INTEL_TGL_12_IDS(&gen11_early_ops),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) INTEL_RKL_IDS(&gen11_early_ops),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) struct resource intel_graphics_stolen_res __ro_after_init = DEFINE_RES_MEM(0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) EXPORT_SYMBOL(intel_graphics_stolen_res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) static void __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) intel_graphics_stolen(int num, int slot, int func,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) const struct intel_early_ops *early_ops)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) resource_size_t base, size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) resource_size_t end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) size = early_ops->stolen_size(num, slot, func);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) base = early_ops->stolen_base(num, slot, func, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) if (!size || !base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) end = base + size - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) intel_graphics_stolen_res.start = base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) intel_graphics_stolen_res.end = end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) printk(KERN_INFO "Reserving Intel graphics memory at %pR\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) &intel_graphics_stolen_res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) /* Mark this space as reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) e820__range_add(base, size, E820_TYPE_RESERVED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) e820__update_table(e820_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) static void __init intel_graphics_quirks(int num, int slot, int func)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) const struct intel_early_ops *early_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) u16 device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) * Reserve "stolen memory" for an integrated GPU. If we've already
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) * found one, there's nothing to do for other (discrete) GPUs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) if (resource_size(&intel_graphics_stolen_res))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) device = read_pci_config_16(num, slot, func, PCI_DEVICE_ID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) for (i = 0; i < ARRAY_SIZE(intel_early_ids); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) kernel_ulong_t driver_data = intel_early_ids[i].driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) if (intel_early_ids[i].device != device)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) early_ops = (typeof(early_ops))driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) intel_graphics_stolen(num, slot, func, early_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) static void __init force_disable_hpet(int num, int slot, int func)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) #ifdef CONFIG_HPET_TIMER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) boot_hpet_disable = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) pr_info("x86/hpet: Will disable the HPET for this platform because it's not reliable\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) #define BCM4331_MMIO_SIZE 16384
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) #define BCM4331_PM_CAP 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) #define bcma_aread32(reg) ioread32(mmio + 1 * BCMA_CORE_SIZE + reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) #define bcma_awrite32(reg, val) iowrite32(val, mmio + 1 * BCMA_CORE_SIZE + reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) static void __init apple_airport_reset(int bus, int slot, int func)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) void __iomem *mmio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) u16 pmcsr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) u64 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) if (!x86_apple_machine)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) /* Card may have been put into PCI_D3hot by grub quirk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) pmcsr = read_pci_config_16(bus, slot, func, BCM4331_PM_CAP + PCI_PM_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) if ((pmcsr & PCI_PM_CTRL_STATE_MASK) != PCI_D0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) write_pci_config_16(bus, slot, func, BCM4331_PM_CAP + PCI_PM_CTRL, pmcsr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) mdelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) pmcsr = read_pci_config_16(bus, slot, func, BCM4331_PM_CAP + PCI_PM_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) if ((pmcsr & PCI_PM_CTRL_STATE_MASK) != PCI_D0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) pr_err("pci 0000:%02x:%02x.%d: Cannot power up Apple AirPort card\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) bus, slot, func);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) addr = read_pci_config(bus, slot, func, PCI_BASE_ADDRESS_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) addr |= (u64)read_pci_config(bus, slot, func, PCI_BASE_ADDRESS_1) << 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) addr &= PCI_BASE_ADDRESS_MEM_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) mmio = early_ioremap(addr, BCM4331_MMIO_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) if (!mmio) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) pr_err("pci 0000:%02x:%02x.%d: Cannot iomap Apple AirPort card\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) bus, slot, func);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) pr_info("Resetting Apple AirPort card (left enabled by EFI)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) for (i = 0; bcma_aread32(BCMA_RESET_ST) && i < 30; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) bcma_awrite32(BCMA_RESET_CTL, BCMA_RESET_CTL_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) bcma_aread32(BCMA_RESET_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) bcma_awrite32(BCMA_RESET_CTL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) bcma_aread32(BCMA_RESET_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) early_iounmap(mmio, BCM4331_MMIO_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) #define QFLAG_APPLY_ONCE 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) #define QFLAG_APPLIED 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) #define QFLAG_DONE (QFLAG_APPLY_ONCE|QFLAG_APPLIED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) struct chipset {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) u32 vendor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) u32 device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) u32 class;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) u32 class_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) u32 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) void (*f)(int num, int slot, int func);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) static struct chipset early_qrk[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) { PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) PCI_CLASS_BRIDGE_PCI, PCI_ANY_ID, QFLAG_APPLY_ONCE, nvidia_bugs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) { PCI_VENDOR_ID_VIA, PCI_ANY_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) PCI_CLASS_BRIDGE_PCI, PCI_ANY_ID, QFLAG_APPLY_ONCE, via_bugs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) { PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_K8_NB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) PCI_CLASS_BRIDGE_HOST, PCI_ANY_ID, 0, fix_hypertransport_config },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP400_SMBUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) PCI_CLASS_SERIAL_SMBUS, PCI_ANY_ID, 0, ati_bugs },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) PCI_CLASS_SERIAL_SMBUS, PCI_ANY_ID, 0, ati_bugs_contd },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) { PCI_VENDOR_ID_INTEL, 0x3403, PCI_CLASS_BRIDGE_HOST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) PCI_BASE_CLASS_BRIDGE, 0, intel_remapping_check },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) { PCI_VENDOR_ID_INTEL, 0x3405, PCI_CLASS_BRIDGE_HOST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) PCI_BASE_CLASS_BRIDGE, 0, intel_remapping_check },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) { PCI_VENDOR_ID_INTEL, 0x3406, PCI_CLASS_BRIDGE_HOST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) PCI_BASE_CLASS_BRIDGE, 0, intel_remapping_check },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA, PCI_ANY_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) 0, intel_graphics_quirks },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) * HPET on the current version of the Baytrail platform has accuracy
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) * problems: it will halt in deep idle state - so we disable it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) * More details can be found in section 18.10.1.3 of the datasheet:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) * http://www.intel.com/content/dam/www/public/us/en/documents/datasheets/atom-z8000-datasheet-vol-1.pdf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) { PCI_VENDOR_ID_INTEL, 0x0f00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) PCI_CLASS_BRIDGE_HOST, PCI_ANY_ID, 0, force_disable_hpet},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) { PCI_VENDOR_ID_BROADCOM, 0x4331,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) PCI_CLASS_NETWORK_OTHER, PCI_ANY_ID, 0, apple_airport_reset},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) static void __init early_pci_scan_bus(int bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) * check_dev_quirk - apply early quirks to a given PCI device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) * @num: bus number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) * @slot: slot number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) * @func: PCI function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) * Check the vendor & device ID against the early quirks table.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) * If the device is single function, let early_pci_scan_bus() know so we don't
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) * poke at this device again.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) static int __init check_dev_quirk(int num, int slot, int func)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) u16 class;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) u16 vendor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) u16 device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) u8 type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) u8 sec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) class = read_pci_config_16(num, slot, func, PCI_CLASS_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) if (class == 0xffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) return -1; /* no class, treat as single function */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) vendor = read_pci_config_16(num, slot, func, PCI_VENDOR_ID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) device = read_pci_config_16(num, slot, func, PCI_DEVICE_ID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) for (i = 0; early_qrk[i].f != NULL; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) if (((early_qrk[i].vendor == PCI_ANY_ID) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) (early_qrk[i].vendor == vendor)) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) ((early_qrk[i].device == PCI_ANY_ID) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) (early_qrk[i].device == device)) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) (!((early_qrk[i].class ^ class) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) early_qrk[i].class_mask))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) if ((early_qrk[i].flags &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) QFLAG_DONE) != QFLAG_DONE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) early_qrk[i].f(num, slot, func);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) early_qrk[i].flags |= QFLAG_APPLIED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) type = read_pci_config_byte(num, slot, func,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) PCI_HEADER_TYPE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) if ((type & 0x7f) == PCI_HEADER_TYPE_BRIDGE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) sec = read_pci_config_byte(num, slot, func, PCI_SECONDARY_BUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) if (sec > num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) early_pci_scan_bus(sec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) if (!(type & 0x80))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) static void __init early_pci_scan_bus(int bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) int slot, func;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) /* Poor man's PCI discovery */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) for (slot = 0; slot < 32; slot++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) for (func = 0; func < 8; func++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) /* Only probe function 0 on single fn devices */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) if (check_dev_quirk(bus, slot, func))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) void __init early_quirks(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) if (!early_pci_allowed())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) early_pci_scan_bus(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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