^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Architecture specific OF callbacks.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #include <linux/export.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/list.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/of_fdt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/libfdt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/of_pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/initrd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <asm/irqdomain.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <asm/hpet.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <asm/apic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <asm/io_apic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <asm/pci_x86.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <asm/setup.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <asm/i8259.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <asm/prom.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) __initdata u64 initial_dtb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) char __initdata cmd_line[COMMAND_LINE_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) int __initdata of_ioapic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) void __init early_init_dt_scan_chosen_arch(unsigned long node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) void __init early_init_dt_add_memory_arch(u64 base, u64 size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) void __init add_dtb(u64 data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) initial_dtb = data + offsetof(struct setup_data, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * CE4100 ids. Will be moved to machine_device_initcall() once we have it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) static struct of_device_id __initdata ce4100_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) { .compatible = "intel,ce4100-cp", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) { .compatible = "isa", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) { .compatible = "pci", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) static int __init add_bus_probe(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) if (!of_have_populated_dt())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) return of_platform_bus_probe(NULL, ce4100_ids, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) device_initcall(add_bus_probe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #ifdef CONFIG_PCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) struct device_node *np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) for_each_node_by_type(np, "pci") {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) const void *prop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) unsigned int bus_min;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) prop = of_get_property(np, "bus-range", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) if (!prop)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) bus_min = be32_to_cpup(prop);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) if (bus->number == bus_min)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) return np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) static int x86_of_pci_irq_enable(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) u32 virq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) u8 pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) ret = pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) if (!pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) virq = of_irq_parse_and_map_pci(dev, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) if (virq == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) dev->irq = virq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) static void x86_of_pci_irq_disable(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) void x86_of_pci_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) pcibios_enable_irq = x86_of_pci_irq_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) pcibios_disable_irq = x86_of_pci_irq_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) static void __init dtb_setup_hpet(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #ifdef CONFIG_HPET_TIMER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) struct device_node *dn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) struct resource r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) dn = of_find_compatible_node(NULL, NULL, "intel,ce4100-hpet");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) if (!dn)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) ret = of_address_to_resource(dn, 0, &r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) WARN_ON(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) hpet_address = r.start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #ifdef CONFIG_X86_LOCAL_APIC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) static void __init dtb_cpu_setup(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) struct device_node *dn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) u32 apic_id, version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) version = GET_APIC_VERSION(apic_read(APIC_LVR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) for_each_of_cpu_node(dn) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) ret = of_property_read_u32(dn, "reg", &apic_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) pr_warn("%pOF: missing local APIC ID\n", dn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) generic_processor_info(apic_id, version);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) static void __init dtb_lapic_setup(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) struct device_node *dn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) struct resource r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) unsigned long lapic_addr = APIC_DEFAULT_PHYS_BASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) dn = of_find_compatible_node(NULL, NULL, "intel,ce4100-lapic");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) if (dn) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) ret = of_address_to_resource(dn, 0, &r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) if (WARN_ON(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) lapic_addr = r.start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) /* Did the boot loader setup the local APIC ? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) if (!boot_cpu_has(X86_FEATURE_APIC)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) if (apic_force_enable(lapic_addr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) smp_found_config = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) pic_mode = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) register_lapic_address(lapic_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #endif /* CONFIG_X86_LOCAL_APIC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #ifdef CONFIG_X86_IO_APIC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) static unsigned int ioapic_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) struct of_ioapic_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) u32 out_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) u32 trigger;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) u32 polarity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) static struct of_ioapic_type of_ioapic_type[] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) .out_type = IRQ_TYPE_EDGE_RISING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) .trigger = IOAPIC_EDGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) .polarity = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) .out_type = IRQ_TYPE_LEVEL_LOW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) .trigger = IOAPIC_LEVEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) .polarity = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) .out_type = IRQ_TYPE_LEVEL_HIGH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) .trigger = IOAPIC_LEVEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) .polarity = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) .out_type = IRQ_TYPE_EDGE_FALLING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) .trigger = IOAPIC_EDGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) .polarity = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) static int dt_irqdomain_alloc(struct irq_domain *domain, unsigned int virq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) unsigned int nr_irqs, void *arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) struct irq_fwspec *fwspec = (struct irq_fwspec *)arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) struct of_ioapic_type *it;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) struct irq_alloc_info tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) int type_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) if (WARN_ON(fwspec->param_count < 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) type_index = fwspec->param[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) if (type_index >= ARRAY_SIZE(of_ioapic_type))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) it = &of_ioapic_type[type_index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) ioapic_set_alloc_attr(&tmp, NUMA_NO_NODE, it->trigger, it->polarity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) tmp.devid = mpc_ioapic_id(mp_irqdomain_ioapic_idx(domain));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) tmp.ioapic.pin = fwspec->param[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) return mp_irqdomain_alloc(domain, virq, nr_irqs, &tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) static const struct irq_domain_ops ioapic_irq_domain_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) .alloc = dt_irqdomain_alloc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) .free = mp_irqdomain_free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) .activate = mp_irqdomain_activate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) .deactivate = mp_irqdomain_deactivate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) static void __init dtb_add_ioapic(struct device_node *dn)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) struct resource r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) struct ioapic_domain_cfg cfg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) .type = IOAPIC_DOMAIN_DYNAMIC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) .ops = &ioapic_irq_domain_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) .dev = dn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) ret = of_address_to_resource(dn, 0, &r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) printk(KERN_ERR "Can't obtain address from device node %pOF.\n", dn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) mp_register_ioapic(++ioapic_id, r.start, gsi_top, &cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) static void __init dtb_ioapic_setup(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) struct device_node *dn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) for_each_compatible_node(dn, NULL, "intel,ce4100-ioapic")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) dtb_add_ioapic(dn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) if (nr_ioapics) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) of_ioapic = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) printk(KERN_ERR "Error: No information about IO-APIC in OF.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) static void __init dtb_ioapic_setup(void) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) static void __init dtb_apic_setup(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #ifdef CONFIG_X86_LOCAL_APIC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) dtb_lapic_setup();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) dtb_cpu_setup();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) dtb_ioapic_setup();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #ifdef CONFIG_OF_EARLY_FLATTREE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) static void __init x86_flattree_get_config(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) u32 size, map_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) void *dt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) if (!initial_dtb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) map_len = max(PAGE_SIZE - (initial_dtb & ~PAGE_MASK), (u64)128);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) dt = early_memremap(initial_dtb, map_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) size = fdt_totalsize(dt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) if (map_len < size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) early_memunmap(dt, map_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) dt = early_memremap(initial_dtb, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) map_len = size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) early_init_dt_verify(dt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) unflatten_and_copy_device_tree();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) early_memunmap(dt, map_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) static inline void x86_flattree_get_config(void) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) void __init x86_dtb_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) x86_flattree_get_config();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) if (!of_have_populated_dt())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) dtb_setup_hpet();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) dtb_apic_setup();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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