^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) #include <linux/sched.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) #include <linux/sched/clock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #include <asm/cpu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <asm/cpufeature.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include "cpu.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define MSR_ZHAOXIN_FCR57 0x00001257
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define ACE_PRESENT (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define ACE_ENABLED (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define ACE_FCR (1 << 7) /* MSR_ZHAOXIN_FCR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define RNG_PRESENT (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define RNG_ENABLED (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define RNG_ENABLE (1 << 8) /* MSR_ZHAOXIN_RNG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) static void init_zhaoxin_cap(struct cpuinfo_x86 *c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) u32 lo, hi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) /* Test for Extended Feature Flags presence */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) if (cpuid_eax(0xC0000000) >= 0xC0000001) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) u32 tmp = cpuid_edx(0xC0000001);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) /* Enable ACE unit, if present and disabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) if ((tmp & (ACE_PRESENT | ACE_ENABLED)) == ACE_PRESENT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) rdmsr(MSR_ZHAOXIN_FCR57, lo, hi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) /* Enable ACE unit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) lo |= ACE_FCR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) wrmsr(MSR_ZHAOXIN_FCR57, lo, hi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) pr_info("CPU: Enabled ACE h/w crypto\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) /* Enable RNG unit, if present and disabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) if ((tmp & (RNG_PRESENT | RNG_ENABLED)) == RNG_PRESENT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) rdmsr(MSR_ZHAOXIN_FCR57, lo, hi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) /* Enable RNG unit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) lo |= RNG_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) wrmsr(MSR_ZHAOXIN_FCR57, lo, hi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) pr_info("CPU: Enabled h/w RNG\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * Store Extended Feature Flags as word 5 of the CPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * capability bit array
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) c->x86_capability[CPUID_C000_0001_EDX] = cpuid_edx(0xC0000001);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) if (c->x86 >= 0x6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) set_cpu_cap(c, X86_FEATURE_REP_GOOD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) static void early_init_zhaoxin(struct cpuinfo_x86 *c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) if (c->x86 >= 0x6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #ifdef CONFIG_X86_64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) set_cpu_cap(c, X86_FEATURE_SYSENTER32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) if (c->x86_power & (1 << 8)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) if (c->cpuid_level >= 0x00000001) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) u32 eax, ebx, ecx, edx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) cpuid(0x00000001, &eax, &ebx, &ecx, &edx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) * If HTT (EDX[28]) is set EBX[16:23] contain the number of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) * apicids which are reserved per package. Store the resulting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) * shift value for the package management code.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) if (edx & (1U << 28))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) c->x86_coreid_bits = get_count_order((ebx >> 16) & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) static void init_zhaoxin(struct cpuinfo_x86 *c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) early_init_zhaoxin(c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) init_intel_cacheinfo(c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) detect_num_cpu_cores(c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #ifdef CONFIG_X86_32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) detect_ht(c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) if (c->cpuid_level > 9) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) unsigned int eax = cpuid_eax(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) * Check for version and the number of counters
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) * Version(eax[7:0]) can't be 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) * Counters(eax[15:8]) should be greater than 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) if ((eax & 0xff) && (((eax >> 8) & 0xff) > 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) set_cpu_cap(c, X86_FEATURE_ARCH_PERFMON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) if (c->x86 >= 0x6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) init_zhaoxin_cap(c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #ifdef CONFIG_X86_64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) init_ia32_feat_ctl(c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #ifdef CONFIG_X86_32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) static unsigned int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) zhaoxin_size_cache(struct cpuinfo_x86 *c, unsigned int size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) return size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) static const struct cpu_dev zhaoxin_cpu_dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) .c_vendor = "zhaoxin",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) .c_ident = { " Shanghai " },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) .c_early_init = early_init_zhaoxin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) .c_init = init_zhaoxin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #ifdef CONFIG_X86_32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) .legacy_cache_size = zhaoxin_size_cache,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) .c_x86_vendor = X86_VENDOR_ZHAOXIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) cpu_dev_register(zhaoxin_cpu_dev);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags