^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) #include <linux/syscore_ops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) #include <linux/suspend.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) #include <linux/cpu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <asm/msr.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <asm/mwait.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define UMWAIT_C02_ENABLE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define UMWAIT_CTRL_VAL(max_time, c02_disable) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) (((max_time) & MSR_IA32_UMWAIT_CONTROL_TIME_MASK) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) ((c02_disable) & MSR_IA32_UMWAIT_CONTROL_C02_DISABLE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * Cache IA32_UMWAIT_CONTROL MSR. This is a systemwide control. By default,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * umwait max time is 100000 in TSC-quanta and C0.2 is enabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) static u32 umwait_control_cached = UMWAIT_CTRL_VAL(100000, UMWAIT_C02_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * Cache the original IA32_UMWAIT_CONTROL MSR value which is configured by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * hardware or BIOS before kernel boot.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) static u32 orig_umwait_control_cached __ro_after_init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * Serialize access to umwait_control_cached and IA32_UMWAIT_CONTROL MSR in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * the sysfs write functions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) static DEFINE_MUTEX(umwait_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) static void umwait_update_control_msr(void * unused)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) lockdep_assert_irqs_disabled();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) wrmsr(MSR_IA32_UMWAIT_CONTROL, READ_ONCE(umwait_control_cached), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * The CPU hotplug callback sets the control MSR to the global control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * Disable interrupts so the read of umwait_control_cached and the WRMSR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * are protected against a concurrent sysfs write. Otherwise the sysfs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * write could update the cached value after it had been read on this CPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * and issue the IPI before the old value had been written. The IPI would
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * interrupt, write the new value and after return from IPI the previous
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * value would be written by this CPU.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * With interrupts disabled the upcoming CPU either sees the new control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * value or the IPI is updating this CPU to the new control value after
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * interrupts have been reenabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) static int umwait_cpu_online(unsigned int cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) local_irq_disable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) umwait_update_control_msr(NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) local_irq_enable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) * The CPU hotplug callback sets the control MSR to the original control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) static int umwait_cpu_offline(unsigned int cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * This code is protected by the CPU hotplug already and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) * orig_umwait_control_cached is never changed after it caches
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * the original control MSR value in umwait_init(). So there
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) * is no race condition here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) wrmsr(MSR_IA32_UMWAIT_CONTROL, orig_umwait_control_cached, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) * On resume, restore IA32_UMWAIT_CONTROL MSR on the boot processor which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) * is the only active CPU at this time. The MSR is set up on the APs via the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) * CPU hotplug callback.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) * This function is invoked on resume from suspend and hibernation. On
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) * resume from suspend the restore should be not required, but we neither
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) * trust the firmware nor does it matter if the same value is written
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) * again.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) static void umwait_syscore_resume(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) umwait_update_control_msr(NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) static struct syscore_ops umwait_syscore_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) .resume = umwait_syscore_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) /* sysfs interface */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) * When bit 0 in IA32_UMWAIT_CONTROL MSR is 1, C0.2 is disabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) * Otherwise, C0.2 is enabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) static inline bool umwait_ctrl_c02_enabled(u32 ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) return !(ctrl & MSR_IA32_UMWAIT_CONTROL_C02_DISABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) static inline u32 umwait_ctrl_max_time(u32 ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) return ctrl & MSR_IA32_UMWAIT_CONTROL_TIME_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) static inline void umwait_update_control(u32 maxtime, bool c02_enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) u32 ctrl = maxtime & MSR_IA32_UMWAIT_CONTROL_TIME_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) if (!c02_enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) ctrl |= MSR_IA32_UMWAIT_CONTROL_C02_DISABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) WRITE_ONCE(umwait_control_cached, ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) /* Propagate to all CPUs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) on_each_cpu(umwait_update_control_msr, NULL, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) static ssize_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) enable_c02_show(struct device *dev, struct device_attribute *attr, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) u32 ctrl = READ_ONCE(umwait_control_cached);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) return sprintf(buf, "%d\n", umwait_ctrl_c02_enabled(ctrl));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) static ssize_t enable_c02_store(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) const char *buf, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) bool c02_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) u32 ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) ret = kstrtobool(buf, &c02_enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) mutex_lock(&umwait_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) ctrl = READ_ONCE(umwait_control_cached);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) if (c02_enable != umwait_ctrl_c02_enabled(ctrl))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) umwait_update_control(ctrl, c02_enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) mutex_unlock(&umwait_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) static DEVICE_ATTR_RW(enable_c02);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) static ssize_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) max_time_show(struct device *kobj, struct device_attribute *attr, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) u32 ctrl = READ_ONCE(umwait_control_cached);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) return sprintf(buf, "%u\n", umwait_ctrl_max_time(ctrl));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) static ssize_t max_time_store(struct device *kobj,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) const char *buf, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) u32 max_time, ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) ret = kstrtou32(buf, 0, &max_time);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) /* bits[1:0] must be zero */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) if (max_time & ~MSR_IA32_UMWAIT_CONTROL_TIME_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) mutex_lock(&umwait_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) ctrl = READ_ONCE(umwait_control_cached);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) if (max_time != umwait_ctrl_max_time(ctrl))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) umwait_update_control(max_time, umwait_ctrl_c02_enabled(ctrl));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) mutex_unlock(&umwait_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) static DEVICE_ATTR_RW(max_time);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) static struct attribute *umwait_attrs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) &dev_attr_enable_c02.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) &dev_attr_max_time.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) static struct attribute_group umwait_attr_group = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) .attrs = umwait_attrs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) .name = "umwait_control",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) static int __init umwait_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) if (!boot_cpu_has(X86_FEATURE_WAITPKG))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) * Cache the original control MSR value before the control MSR is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) * changed. This is the only place where orig_umwait_control_cached
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) * is modified.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) rdmsrl(MSR_IA32_UMWAIT_CONTROL, orig_umwait_control_cached);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) ret = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "umwait:online",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) umwait_cpu_online, umwait_cpu_offline);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) * On failure, the control MSR on all CPUs has the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) * original control value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) register_syscore_ops(&umwait_syscore_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) * Add umwait control interface. Ignore failure, so at least the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) * default values are set up in case the machine manages to boot.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) dev = cpu_subsys.dev_root;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) return sysfs_create_group(&dev->kobj, &umwait_attr_group);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) device_initcall(umwait_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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