Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Hygon Processor Support for Linux
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (C) 2018 Chengdu Haiguang IC Design Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * Author: Pu Wen <puwen@hygon.cn>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <asm/cpu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <asm/smp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <asm/numa.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <asm/cacheinfo.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <asm/spec-ctrl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <asm/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #ifdef CONFIG_X86_64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) # include <asm/set_memory.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include "cpu.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define APICID_SOCKET_ID_BIT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26)  * nodes_per_socket: Stores the number of nodes per socket.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27)  * Refer to CPUID Fn8000_001E_ECX Node Identifiers[10:8]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) static u32 nodes_per_socket = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #ifdef CONFIG_NUMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33)  * To workaround broken NUMA config.  Read the comment in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34)  * srat_detect_node().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) static int nearby_node(int apicid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	int i, node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	for (i = apicid - 1; i >= 0; i--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 		node = __apicid_to_node[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 		if (node != NUMA_NO_NODE && node_online(node))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 			return node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	for (i = apicid + 1; i < MAX_LOCAL_APIC; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 		node = __apicid_to_node[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 		if (node != NUMA_NO_NODE && node_online(node))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 			return node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	return first_node(node_online_map); /* Shouldn't happen */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) static void hygon_get_topology_early(struct cpuinfo_x86 *c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	if (cpu_has(c, X86_FEATURE_TOPOEXT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 		smp_num_siblings = ((cpuid_ebx(0x8000001e) >> 8) & 0xff) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61)  * Fixup core topology information for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62)  * (1) Hygon multi-node processors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63)  *     Assumption: Number of cores in each internal node is the same.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64)  * (2) Hygon processors supporting compute units
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) static void hygon_get_topology(struct cpuinfo_x86 *c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	int cpu = smp_processor_id();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	/* get information required for multi-node processors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	if (boot_cpu_has(X86_FEATURE_TOPOEXT)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 		int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 		u32 eax, ebx, ecx, edx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 		cpuid(0x8000001e, &eax, &ebx, &ecx, &edx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 		c->cpu_die_id  = ecx & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 		c->cpu_core_id = ebx & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 		if (smp_num_siblings > 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 			c->x86_max_cores /= smp_num_siblings;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 		 * In case leaf B is available, use it to derive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 		 * topology information.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 		err = detect_extended_topology(c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 		if (!err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 			c->x86_coreid_bits = get_count_order(c->x86_max_cores);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 		/* Socket ID is ApicId[6] for these processors. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 		c->phys_proc_id = c->apicid >> APICID_SOCKET_ID_BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 		cacheinfo_hygon_init_llc_id(c, cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	} else if (cpu_has(c, X86_FEATURE_NODEID_MSR)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 		u64 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 		rdmsrl(MSR_FAM10H_NODE_ID, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 		c->cpu_die_id = value & 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 		per_cpu(cpu_llc_id, cpu) = c->cpu_die_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	} else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	if (nodes_per_socket > 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 		set_cpu_cap(c, X86_FEATURE_AMD_DCM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)  * On Hygon setup the lower bits of the APIC id distinguish the cores.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)  * Assumes number of cores is a power of two.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) static void hygon_detect_cmp(struct cpuinfo_x86 *c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	unsigned int bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	int cpu = smp_processor_id();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	bits = c->x86_coreid_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	/* Low order bits define the core id (index of core in socket) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	c->cpu_core_id = c->initial_apicid & ((1 << bits)-1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	/* Convert the initial APIC ID into the socket ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	c->phys_proc_id = c->initial_apicid >> bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	/* use socket ID also for last level cache */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	per_cpu(cpu_llc_id, cpu) = c->cpu_die_id = c->phys_proc_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) static void srat_detect_node(struct cpuinfo_x86 *c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #ifdef CONFIG_NUMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	int cpu = smp_processor_id();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	int node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	unsigned int apicid = c->apicid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	node = numa_cpu_node(cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	if (node == NUMA_NO_NODE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 		node = per_cpu(cpu_llc_id, cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	 * On multi-fabric platform (e.g. Numascale NumaChip) a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	 * platform-specific handler needs to be called to fixup some
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	 * IDs of the CPU.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	if (x86_cpuinit.fixup_cpu_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 		x86_cpuinit.fixup_cpu_id(c, node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	if (!node_online(node)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 		 * Two possibilities here:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 		 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 		 * - The CPU is missing memory and no node was created.  In
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 		 *   that case try picking one from a nearby CPU.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 		 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 		 * - The APIC IDs differ from the HyperTransport node IDs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 		 *   Assume they are all increased by a constant offset, but
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 		 *   in the same order as the HT nodeids.  If that doesn't
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 		 *   result in a usable node fall back to the path for the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 		 *   previous case.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 		 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 		 * This workaround operates directly on the mapping between
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 		 * APIC ID and NUMA node, assuming certain relationship
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 		 * between APIC ID, HT node ID and NUMA topology.  As going
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 		 * through CPU mapping may alter the outcome, directly
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 		 * access __apicid_to_node[].
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 		int ht_nodeid = c->initial_apicid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 		if (__apicid_to_node[ht_nodeid] != NUMA_NO_NODE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 			node = __apicid_to_node[ht_nodeid];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 		/* Pick a nearby node */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 		if (!node_online(node))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 			node = nearby_node(apicid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	numa_set_node(cpu, node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) static void early_init_hygon_mc(struct cpuinfo_x86 *c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #ifdef CONFIG_SMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	unsigned int bits, ecx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	/* Multi core CPU? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	if (c->extended_cpuid_level < 0x80000008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	ecx = cpuid_ecx(0x80000008);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	c->x86_max_cores = (ecx & 0xff) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	/* CPU telling us the core id bits shift? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	bits = (ecx >> 12) & 0xF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	/* Otherwise recompute */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	if (bits == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 		while ((1 << bits) < c->x86_max_cores)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 			bits++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	c->x86_coreid_bits = bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) static void bsp_init_hygon(struct cpuinfo_x86 *c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #ifdef CONFIG_X86_64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	unsigned long long tseg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	 * Split up direct mapping around the TSEG SMM area.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	 * Don't do it for gbpages because there seems very little
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	 * benefit in doing so.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	if (!rdmsrl_safe(MSR_K8_TSEG_ADDR, &tseg)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 		unsigned long pfn = tseg >> PAGE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 		pr_debug("tseg: %010llx\n", tseg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 		if (pfn_range_is_mapped(pfn, pfn + 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 			set_memory_4k((unsigned long)__va(tseg), 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	if (cpu_has(c, X86_FEATURE_CONSTANT_TSC)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 		u64 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 		rdmsrl(MSR_K7_HWCR, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 		if (!(val & BIT(24)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 			pr_warn(FW_BUG "TSC doesn't count with P0 frequency!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	if (cpu_has(c, X86_FEATURE_MWAITX))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 		use_mwaitx_delay();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	if (boot_cpu_has(X86_FEATURE_TOPOEXT)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 		u32 ecx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 		ecx = cpuid_ecx(0x8000001e);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 		nodes_per_socket = ((ecx >> 8) & 7) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	} else if (boot_cpu_has(X86_FEATURE_NODEID_MSR)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 		u64 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 		rdmsrl(MSR_FAM10H_NODE_ID, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 		nodes_per_socket = ((value >> 3) & 7) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	if (!boot_cpu_has(X86_FEATURE_AMD_SSBD) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	    !boot_cpu_has(X86_FEATURE_VIRT_SSBD)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 		 * Try to cache the base value so further operations can
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 		 * avoid RMW. If that faults, do not enable SSBD.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 		if (!rdmsrl_safe(MSR_AMD64_LS_CFG, &x86_amd_ls_cfg_base)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 			setup_force_cpu_cap(X86_FEATURE_LS_CFG_SSBD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 			setup_force_cpu_cap(X86_FEATURE_SSBD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 			x86_amd_ls_cfg_ssbd_mask = 1ULL << 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) static void early_init_hygon(struct cpuinfo_x86 *c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	u32 dummy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	early_init_hygon_mc(c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	set_cpu_cap(c, X86_FEATURE_K8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	rdmsr_safe(MSR_AMD64_PATCH_LEVEL, &c->microcode, &dummy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	 * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	 * with P/T states and does not stop in deep C-states
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	if (c->x86_power & (1 << 8)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 		set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 		set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	/* Bit 12 of 8000_0007 edx is accumulated power mechanism. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	if (c->x86_power & BIT(12))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 		set_cpu_cap(c, X86_FEATURE_ACC_POWER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #ifdef CONFIG_X86_64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	set_cpu_cap(c, X86_FEATURE_SYSCALL32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_PCI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	 * ApicID can always be treated as an 8-bit value for Hygon APIC So, we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	 * can safely set X86_FEATURE_EXTD_APICID unconditionally.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	if (boot_cpu_has(X86_FEATURE_APIC))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 		set_cpu_cap(c, X86_FEATURE_EXTD_APICID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	 * This is only needed to tell the kernel whether to use VMCALL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	 * and VMMCALL.  VMMCALL is never executed except under virt, so
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	 * we can set it unconditionally.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	set_cpu_cap(c, X86_FEATURE_VMMCALL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	hygon_get_topology_early(c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) static void init_hygon(struct cpuinfo_x86 *c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	early_init_hygon(c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	 * Bit 31 in normal CPUID used for nonstandard 3DNow ID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	 * 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	clear_cpu_cap(c, 0*32+31);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	set_cpu_cap(c, X86_FEATURE_REP_GOOD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 	/* get apicid instead of initial apic id from cpuid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	c->apicid = hard_smp_processor_id();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	set_cpu_cap(c, X86_FEATURE_ZEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	set_cpu_cap(c, X86_FEATURE_CPB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	cpu_detect_cache_sizes(c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	hygon_detect_cmp(c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	hygon_get_topology(c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	srat_detect_node(c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	init_hygon_cacheinfo(c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 	if (cpu_has(c, X86_FEATURE_XMM2)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 		 * Use LFENCE for execution serialization.  On families which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 		 * don't have that MSR, LFENCE is already serializing.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 		 * msr_set_bit() uses the safe accessors, too, even if the MSR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 		 * is not present.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 		msr_set_bit(MSR_F10H_DECFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 			    MSR_F10H_DECFG_LFENCE_SERIALIZE_BIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 		/* A serializing LFENCE stops RDTSC speculation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 		set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 	 * Hygon processors have APIC timer running in deep C states.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 	set_cpu_cap(c, X86_FEATURE_ARAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 	/* Hygon CPUs don't reset SS attributes on SYSRET, Xen does. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 	if (!cpu_has(c, X86_FEATURE_XENPV))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 		set_cpu_bug(c, X86_BUG_SYSRET_SS_ATTRS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 	check_null_seg_clears_base(c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) static void cpu_detect_tlb_hygon(struct cpuinfo_x86 *c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 	u32 ebx, eax, ecx, edx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 	u16 mask = 0xfff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 	if (c->extended_cpuid_level < 0x80000006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 	cpuid(0x80000006, &eax, &ebx, &ecx, &edx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 	tlb_lld_4k[ENTRIES] = (ebx >> 16) & mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 	tlb_lli_4k[ENTRIES] = ebx & mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 	/* Handle DTLB 2M and 4M sizes, fall back to L1 if L2 is disabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 	if (!((eax >> 16) & mask))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 		tlb_lld_2m[ENTRIES] = (cpuid_eax(0x80000005) >> 16) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 		tlb_lld_2m[ENTRIES] = (eax >> 16) & mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 	/* a 4M entry uses two 2M entries */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 	tlb_lld_4m[ENTRIES] = tlb_lld_2m[ENTRIES] >> 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 	/* Handle ITLB 2M and 4M sizes, fall back to L1 if L2 is disabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 	if (!(eax & mask)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 		cpuid(0x80000005, &eax, &ebx, &ecx, &edx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 		tlb_lli_2m[ENTRIES] = eax & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 	} else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 		tlb_lli_2m[ENTRIES] = eax & mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 	tlb_lli_4m[ENTRIES] = tlb_lli_2m[ENTRIES] >> 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) static const struct cpu_dev hygon_cpu_dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 	.c_vendor	= "Hygon",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 	.c_ident	= { "HygonGenuine" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 	.c_early_init   = early_init_hygon,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 	.c_detect_tlb	= cpu_detect_tlb_hygon,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 	.c_bsp_init	= bsp_init_hygon,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 	.c_init		= init_hygon,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 	.c_x86_vendor	= X86_VENDOR_HYGON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) cpu_dev_register(hygon_cpu_dev);