Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) #include <asm/dma.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #include <asm/processor-cyrix.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <asm/processor-flags.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/timer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <asm/pci-direct.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <asm/tsc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <asm/cpufeature.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/sched.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/sched/clock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include "cpu.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19)  * Read NSC/Cyrix DEVID registers (DIR) to get more detailed info. about the CPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) static void __do_cyrix_devid(unsigned char *dir0, unsigned char *dir1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 	unsigned char ccr2, ccr3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 	/* we test for DEVID by checking whether CCR3 is writable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 	ccr3 = getCx86(CX86_CCR3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 	setCx86(CX86_CCR3, ccr3 ^ 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 	getCx86(0xc0);   /* dummy to change bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 	if (getCx86(CX86_CCR3) == ccr3) {       /* no DEVID regs. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 		ccr2 = getCx86(CX86_CCR2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 		setCx86(CX86_CCR2, ccr2 ^ 0x04);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 		getCx86(0xc0);  /* dummy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 		if (getCx86(CX86_CCR2) == ccr2) /* old Cx486SLC/DLC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 			*dir0 = 0xfd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 		else {                          /* Cx486S A step */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 			setCx86(CX86_CCR2, ccr2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 			*dir0 = 0xfe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 		setCx86(CX86_CCR3, ccr3);  /* restore CCR3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 		/* read DIR0 and DIR1 CPU registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 		*dir0 = getCx86(CX86_DIR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 		*dir1 = getCx86(CX86_DIR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) static void do_cyrix_devid(unsigned char *dir0, unsigned char *dir1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	local_irq_save(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	__do_cyrix_devid(dir0, dir1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	local_irq_restore(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59)  * Cx86_dir0_msb is a HACK needed by check_cx686_cpuid/slop in bugs.h in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60)  * order to identify the Cyrix CPU model after we're out of setup.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62)  * Actually since bugs.h doesn't even reference this perhaps someone should
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63)  * fix the documentation ???
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) static unsigned char Cx86_dir0_msb = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) static const char Cx86_model[][9] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	"Cx486", "Cx486", "5x86 ", "6x86", "MediaGX ", "6x86MX ",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	"M II ", "Unknown"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) static const char Cx486_name[][5] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	"SLC", "DLC", "SLC2", "DLC2", "SRx", "DRx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	"SRx2", "DRx2"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) static const char Cx486S_name[][4] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	"S", "S2", "Se", "S2e"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) static const char Cx486D_name[][4] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	"DX", "DX2", "?", "?", "?", "DX4"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) static char Cx86_cb[] = "?.5x Core/Bus Clock";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) static const char cyrix_model_mult1[] = "12??43";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) static const char cyrix_model_mult2[] = "12233445";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86)  * Reset the slow-loop (SLOP) bit on the 686(L) which is set by some old
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87)  * BIOSes for compatibility with DOS games.  This makes the udelay loop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88)  * work correctly, and improves performance.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90)  * FIXME: our newer udelay uses the tsc. We don't need to frob with SLOP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) static void check_cx686_slop(struct cpuinfo_x86 *c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	if (Cx86_dir0_msb == 3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 		unsigned char ccr3, ccr5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 		local_irq_save(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 		ccr3 = getCx86(CX86_CCR3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 		setCx86(CX86_CCR3, (ccr3 & 0x0f) | 0x10); /* enable MAPEN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 		ccr5 = getCx86(CX86_CCR5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 		if (ccr5 & 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 			setCx86(CX86_CCR5, ccr5 & 0xfd);  /* reset SLOP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 		setCx86(CX86_CCR3, ccr3);                 /* disable MAPEN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 		local_irq_restore(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 		if (ccr5 & 2) { /* possible wrong calibration done */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 			pr_info("Recalibrating delay loop with SLOP bit reset\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 			calibrate_delay();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 			c->loops_per_jiffy = loops_per_jiffy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) static void set_cx86_reorder(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	u8 ccr3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	pr_info("Enable Memory access reorder on Cyrix/NSC processor.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	ccr3 = getCx86(CX86_CCR3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	setCx86(CX86_CCR3, (ccr3 & 0x0f) | 0x10); /* enable MAPEN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	/* Load/Store Serialize to mem access disable (=reorder it) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	setCx86(CX86_PCR0, getCx86(CX86_PCR0) & ~0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	/* set load/store serialize from 1GB to 4GB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	ccr3 |= 0xe0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	setCx86(CX86_CCR3, ccr3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) static void set_cx86_memwb(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	pr_info("Enable Memory-Write-back mode on Cyrix/NSC processor.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	/* CCR2 bit 2: unlock NW bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	setCx86(CX86_CCR2, getCx86(CX86_CCR2) & ~0x04);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	/* set 'Not Write-through' */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	write_cr0(read_cr0() | X86_CR0_NW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	/* CCR2 bit 2: lock NW bit and set WT1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	setCx86(CX86_CCR2, getCx86(CX86_CCR2) | 0x14);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)  *	Configure later MediaGX and/or Geode processor.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) static void geode_configure(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	u8 ccr3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	local_irq_save(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	/* Suspend on halt power saving and enable #SUSP pin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	setCx86(CX86_CCR2, getCx86(CX86_CCR2) | 0x88);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	ccr3 = getCx86(CX86_CCR3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	setCx86(CX86_CCR3, (ccr3 & 0x0f) | 0x10);	/* enable MAPEN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	/* FPU fast, DTE cache, Mem bypass */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	setCx86(CX86_CCR4, getCx86(CX86_CCR4) | 0x38);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	setCx86(CX86_CCR3, ccr3);			/* disable MAPEN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	set_cx86_memwb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	set_cx86_reorder();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	local_irq_restore(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) static void early_init_cyrix(struct cpuinfo_x86 *c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	unsigned char dir0, dir0_msn, dir1 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	__do_cyrix_devid(&dir0, &dir1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	dir0_msn = dir0 >> 4; /* identifies CPU "family"   */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	switch (dir0_msn) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	case 3: /* 6x86/6x86L */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 		/* Emulate MTRRs using Cyrix's ARRs. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 		set_cpu_cap(c, X86_FEATURE_CYRIX_ARR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	case 5: /* 6x86MX/M II */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 		/* Emulate MTRRs using Cyrix's ARRs. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 		set_cpu_cap(c, X86_FEATURE_CYRIX_ARR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) static void init_cyrix(struct cpuinfo_x86 *c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	unsigned char dir0, dir0_msn, dir0_lsn, dir1 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	char *buf = c->x86_model_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	const char *p = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	 * Bit 31 in normal CPUID used for nonstandard 3DNow ID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	 * 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	clear_cpu_cap(c, 0*32+31);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	/* Cyrix used bit 24 in extended (AMD) CPUID for Cyrix MMX extensions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	if (test_cpu_cap(c, 1*32+24)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 		clear_cpu_cap(c, 1*32+24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 		set_cpu_cap(c, X86_FEATURE_CXMMX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	do_cyrix_devid(&dir0, &dir1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	check_cx686_slop(c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	Cx86_dir0_msb = dir0_msn = dir0 >> 4; /* identifies CPU "family"   */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	dir0_lsn = dir0 & 0xf;                /* model or clock multiplier */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	/* common case step number/rev -- exceptions handled below */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	c->x86_model = (dir1 >> 4) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	c->x86_stepping = dir1 & 0xf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	/* Now cook; the original recipe is by Channing Corn, from Cyrix.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	 * We do the same thing for each generation: we work out
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	 * the model, multiplier and stepping.  Black magic included,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	 * to make the silicon step/rev numbers match the printed ones.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	switch (dir0_msn) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 		unsigned char tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	case 0: /* Cx486SLC/DLC/SRx/DRx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 		p = Cx486_name[dir0_lsn & 7];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	case 1: /* Cx486S/DX/DX2/DX4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 		p = (dir0_lsn & 8) ? Cx486D_name[dir0_lsn & 5]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 			: Cx486S_name[dir0_lsn & 3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	case 2: /* 5x86 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 		Cx86_cb[2] = cyrix_model_mult1[dir0_lsn & 5];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 		p = Cx86_cb+2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	case 3: /* 6x86/6x86L */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 		Cx86_cb[1] = ' ';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 		Cx86_cb[2] = cyrix_model_mult1[dir0_lsn & 5];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 		if (dir1 > 0x21) { /* 686L */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 			Cx86_cb[0] = 'L';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 			p = Cx86_cb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 			(c->x86_model)++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 		} else             /* 686 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 			p = Cx86_cb+1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 		/* Emulate MTRRs using Cyrix's ARRs. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 		set_cpu_cap(c, X86_FEATURE_CYRIX_ARR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 		/* 6x86's contain this bug */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 		set_cpu_bug(c, X86_BUG_COMA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	case 4: /* MediaGX/GXm or Geode GXM/GXLV/GX1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	case 11: /* GX1 with inverted Device ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #ifdef CONFIG_PCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 		u32 vendor, device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 		 * It isn't really a PCI quirk directly, but the cure is the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 		 * same. The MediaGX has deep magic SMM stuff that handles the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 		 * SB emulation. It throws away the fifo on disable_dma() which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 		 * is wrong and ruins the audio.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 		 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 		 *  Bug2: VSA1 has a wrap bug so that using maximum sized DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 		 *  causes bad things. According to NatSemi VSA2 has another
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 		 *  bug to do with 'hlt'. I've not seen any boards using VSA2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 		 *  and X doesn't seem to support it either so who cares 8).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 		 *  VSA1 we work around however.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 		pr_info("Working around Cyrix MediaGX virtual DMA bugs.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 		isa_dma_bridge_buggy = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 		/* We do this before the PCI layer is running. However we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 		   are safe here as we know the bridge must be a Cyrix
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 		   companion and must be present */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 		vendor = read_pci_config_16(0, 0, 0x12, PCI_VENDOR_ID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 		device = read_pci_config_16(0, 0, 0x12, PCI_DEVICE_ID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 		 *  The 5510/5520 companion chips have a funky PIT.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 		if (vendor == PCI_VENDOR_ID_CYRIX &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 			(device == PCI_DEVICE_ID_CYRIX_5510 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 					device == PCI_DEVICE_ID_CYRIX_5520))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 			mark_tsc_unstable("cyrix 5510/5520 detected");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 		c->x86_cache_size = 16;	/* Yep 16K integrated cache thats it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 		/* GXm supports extended cpuid levels 'ala' AMD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 		if (c->cpuid_level == 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 			/* Enable cxMMX extensions (GX1 Datasheet 54) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 			setCx86(CX86_CCR7, getCx86(CX86_CCR7) | 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 			/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 			 * GXm : 0x30 ... 0x5f GXm  datasheet 51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 			 * GXlv: 0x6x          GXlv datasheet 54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 			 *  ?  : 0x7x
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 			 * GX1 : 0x8x          GX1  datasheet 56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 			 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 			if ((0x30 <= dir1 && dir1 <= 0x6f) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 					(0x80 <= dir1 && dir1 <= 0x8f))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 				geode_configure();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 			return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 		} else { /* MediaGX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 			Cx86_cb[2] = (dir0_lsn & 1) ? '3' : '4';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 			p = Cx86_cb+2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 			c->x86_model = (dir1 & 0x20) ? 1 : 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 	case 5: /* 6x86MX/M II */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 		if (dir1 > 7) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 			dir0_msn++;  /* M II */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 			/* Enable MMX extensions (App note 108) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 			setCx86(CX86_CCR7, getCx86(CX86_CCR7)|1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 		} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 			/* A 6x86MX - it has the bug. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 			set_cpu_bug(c, X86_BUG_COMA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 		tmp = (!(dir0_lsn & 7) || dir0_lsn & 1) ? 2 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 		Cx86_cb[tmp] = cyrix_model_mult2[dir0_lsn & 7];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 		p = Cx86_cb+tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 		if (((dir1 & 0x0f) > 4) || ((dir1 & 0xf0) == 0x20))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 			(c->x86_model)++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 		/* Emulate MTRRs using Cyrix's ARRs. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 		set_cpu_cap(c, X86_FEATURE_CYRIX_ARR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 	case 0xf:  /* Cyrix 486 without DEVID registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 		switch (dir0_lsn) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 		case 0xd:  /* either a 486SLC or DLC w/o DEVID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 			dir0_msn = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 			p = Cx486_name[!!boot_cpu_has(X86_FEATURE_FPU)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 		case 0xe:  /* a 486S A step */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 			dir0_msn = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 			p = Cx486S_name[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 	default:  /* unknown (shouldn't happen, we know everyone ;-) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 		dir0_msn = 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 	strcpy(buf, Cx86_model[dir0_msn & 7]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 	if (p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 		strcat(buf, p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 	return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)  * Handle National Semiconductor branded processors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) static void init_nsc(struct cpuinfo_x86 *c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 	 * There may be GX1 processors in the wild that are branded
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 	 * NSC and not Cyrix.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 	 * This function only handles the GX processor, and kicks every
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 	 * thing else to the Cyrix init function above - that should
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 	 * cover any processors that might have been branded differently
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 	 * after NSC acquired Cyrix.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 	 * If this breaks your GX1 horribly, please e-mail
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 	 * info-linux@ldcmail.amd.com to tell us.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 	/* Handle the GX (Formally known as the GX2) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 	if (c->x86 == 5 && c->x86_model == 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 		cpu_detect_cache_sizes(c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 		init_cyrix(c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)  * Cyrix CPUs without cpuid or with cpuid not yet enabled can be detected
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)  * by the fact that they preserve the flags across the division of 5/2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)  * PII and PPro exhibit this behavior too, but they have cpuid available.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)  * Perform the Cyrix 5/2 test. A Cyrix won't change
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)  * the flags, while other 486 chips will.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) static inline int test_cyrix_52div(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 	unsigned int test;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 	__asm__ __volatile__(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 	     "sahf\n\t"		/* clear flags (%eax = 0x0005) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 	     "div %b2\n\t"	/* divide 5 by 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 	     "lahf"		/* store flags into %ah */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 	     : "=a" (test)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 	     : "0" (5), "q" (2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 	     : "cc");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 	/* AH is 0x02 on Cyrix after the divide.. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 	return (unsigned char) (test >> 8) == 0x02;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) static void cyrix_identify(struct cpuinfo_x86 *c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 	/* Detect Cyrix with disabled CPUID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) 	if (c->x86 == 4 && test_cyrix_52div()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 		unsigned char dir0, dir1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) 		strcpy(c->x86_vendor_id, "CyrixInstead");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 		c->x86_vendor = X86_VENDOR_CYRIX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 		/* Actually enable cpuid on the older cyrix */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) 		/* Retrieve CPU revisions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) 		do_cyrix_devid(&dir0, &dir1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) 		dir0 >>= 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) 		/* Check it is an affected model */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) 		if (dir0 == 5 || dir0 == 3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) 			unsigned char ccr3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) 			unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) 			pr_info("Enabling CPUID on Cyrix processor.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) 			local_irq_save(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) 			ccr3 = getCx86(CX86_CCR3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) 			/* enable MAPEN  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) 			setCx86(CX86_CCR3, (ccr3 & 0x0f) | 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) 			/* enable cpuid  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) 			setCx86(CX86_CCR4, getCx86(CX86_CCR4) | 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) 			/* disable MAPEN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) 			setCx86(CX86_CCR3, ccr3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) 			local_irq_restore(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) static const struct cpu_dev cyrix_cpu_dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) 	.c_vendor	= "Cyrix",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) 	.c_ident	= { "CyrixInstead" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) 	.c_early_init	= early_init_cyrix,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) 	.c_init		= init_cyrix,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) 	.c_identify	= cyrix_identify,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) 	.c_x86_vendor	= X86_VENDOR_CYRIX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) cpu_dev_register(cyrix_cpu_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) static const struct cpu_dev nsc_cpu_dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) 	.c_vendor	= "NSC",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) 	.c_ident	= { "Geode by NSC" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) 	.c_init		= init_nsc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) 	.c_x86_vendor	= X86_VENDOR_NSC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) cpu_dev_register(nsc_cpu_dev);