Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) #ifndef ARCH_X86_CPU_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) #define ARCH_X86_CPU_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) /* attempt to consolidate cpu attributes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) struct cpu_dev {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) 	const char	*c_vendor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) 	/* some have two possibilities for cpuid string */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 	const char	*c_ident[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 	void            (*c_early_init)(struct cpuinfo_x86 *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 	void		(*c_bsp_init)(struct cpuinfo_x86 *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 	void		(*c_init)(struct cpuinfo_x86 *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 	void		(*c_identify)(struct cpuinfo_x86 *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 	void		(*c_detect_tlb)(struct cpuinfo_x86 *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 	int		c_x86_vendor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #ifdef CONFIG_X86_32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 	/* Optional vendor specific routine to obtain the cache size. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 	unsigned int	(*legacy_cache_size)(struct cpuinfo_x86 *,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 					     unsigned int);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 	/* Family/stepping-based lookup table for model names. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 	struct legacy_cpu_model_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 		int		family;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 		const char	*model_names[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 	}		legacy_models[5];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) struct _tlb_table {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 	unsigned char descriptor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 	char tlb_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 	unsigned int entries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 	/* unsigned int ways; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 	char info[128];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define cpu_dev_register(cpu_devX) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 	static const struct cpu_dev *const __cpu_dev_##cpu_devX __used \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 	__section(".x86_cpu_dev.init") = \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 	&cpu_devX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) extern const struct cpu_dev *const __x86_cpu_dev_start[],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 			    *const __x86_cpu_dev_end[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #ifdef CONFIG_CPU_SUP_INTEL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) enum tsx_ctrl_states {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 	TSX_CTRL_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 	TSX_CTRL_DISABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 	TSX_CTRL_NOT_SUPPORTED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) extern __ro_after_init enum tsx_ctrl_states tsx_ctrl_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) extern void __init tsx_init(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) extern void tsx_enable(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) extern void tsx_disable(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) static inline void tsx_init(void) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #endif /* CONFIG_CPU_SUP_INTEL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) extern void get_cpu_cap(struct cpuinfo_x86 *c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) extern void get_cpu_address_sizes(struct cpuinfo_x86 *c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) extern void cpu_detect_cache_sizes(struct cpuinfo_x86 *c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) extern void init_scattered_cpuid_features(struct cpuinfo_x86 *c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) extern void init_intel_cacheinfo(struct cpuinfo_x86 *c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) extern void init_amd_cacheinfo(struct cpuinfo_x86 *c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) extern void init_hygon_cacheinfo(struct cpuinfo_x86 *c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) extern void detect_num_cpu_cores(struct cpuinfo_x86 *c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) extern int detect_extended_topology_early(struct cpuinfo_x86 *c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) extern int detect_extended_topology(struct cpuinfo_x86 *c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) extern int detect_ht_early(struct cpuinfo_x86 *c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) extern void detect_ht(struct cpuinfo_x86 *c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) extern void check_null_seg_clears_base(struct cpuinfo_x86 *c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) unsigned int aperfmperf_get_khz(int cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) extern void x86_spec_ctrl_setup_ap(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) extern void update_srbds_msr(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) extern u64 x86_read_arch_cap_msr(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #endif /* ARCH_X86_CPU_H */