Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3) #include <linux/sched.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4) #include <linux/sched/clock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) #include <asm/cpu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #include <asm/cpufeature.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <asm/e820/api.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <asm/mtrr.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <asm/msr.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include "cpu.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #define ACE_PRESENT	(1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #define ACE_ENABLED	(1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #define ACE_FCR		(1 << 28)	/* MSR_VIA_FCR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define RNG_PRESENT	(1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define RNG_ENABLED	(1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define RNG_ENABLE	(1 << 6)	/* MSR_VIA_RNG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) static void init_c3(struct cpuinfo_x86 *c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 	u32  lo, hi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 	/* Test for Centaur Extended Feature Flags presence */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 	if (cpuid_eax(0xC0000000) >= 0xC0000001) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 		u32 tmp = cpuid_edx(0xC0000001);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 		/* enable ACE unit, if present and disabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 		if ((tmp & (ACE_PRESENT | ACE_ENABLED)) == ACE_PRESENT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 			rdmsr(MSR_VIA_FCR, lo, hi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 			lo |= ACE_FCR;		/* enable ACE unit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 			wrmsr(MSR_VIA_FCR, lo, hi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 			pr_info("CPU: Enabled ACE h/w crypto\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 		/* enable RNG unit, if present and disabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 		if ((tmp & (RNG_PRESENT | RNG_ENABLED)) == RNG_PRESENT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 			rdmsr(MSR_VIA_RNG, lo, hi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 			lo |= RNG_ENABLE;	/* enable RNG unit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 			wrmsr(MSR_VIA_RNG, lo, hi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 			pr_info("CPU: Enabled h/w RNG\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 		/* store Centaur Extended Feature Flags as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 		 * word 5 of the CPU capability bit array
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 		c->x86_capability[CPUID_C000_0001_EDX] = cpuid_edx(0xC0000001);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #ifdef CONFIG_X86_32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	/* Cyrix III family needs CX8 & PGE explicitly enabled. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	if (c->x86_model >= 6 && c->x86_model <= 13) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 		rdmsr(MSR_VIA_FCR, lo, hi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 		lo |= (1<<1 | 1<<7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 		wrmsr(MSR_VIA_FCR, lo, hi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 		set_cpu_cap(c, X86_FEATURE_CX8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	/* Before Nehemiah, the C3's had 3dNOW! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	if (c->x86_model >= 6 && c->x86_model < 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 		set_cpu_cap(c, X86_FEATURE_3DNOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	if (c->x86 == 0x6 && c->x86_model >= 0xf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 		c->x86_cache_alignment = c->x86_clflush_size * 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 		set_cpu_cap(c, X86_FEATURE_REP_GOOD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	if (c->x86 >= 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 		set_cpu_cap(c, X86_FEATURE_REP_GOOD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 		ECX8		= 1<<1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 		EIERRINT	= 1<<2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 		DPM		= 1<<3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 		DMCE		= 1<<4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 		DSTPCLK		= 1<<5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 		ELINEAR		= 1<<6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 		DSMC		= 1<<7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 		DTLOCK		= 1<<8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 		EDCTLB		= 1<<8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 		EMMX		= 1<<9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 		DPDC		= 1<<11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 		EBRPRED		= 1<<12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 		DIC		= 1<<13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 		DDC		= 1<<14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 		DNA		= 1<<15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 		ERETSTK		= 1<<16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 		E2MMX		= 1<<19,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 		EAMD3D		= 1<<20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) static void early_init_centaur(struct cpuinfo_x86 *c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) #ifdef CONFIG_X86_32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	/* Emulate MTRRs using Centaur's MCR. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	if (c->x86 == 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 		set_cpu_cap(c, X86_FEATURE_CENTAUR_MCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	if ((c->x86 == 6 && c->x86_model >= 0xf) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	    (c->x86 >= 7))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 		set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #ifdef CONFIG_X86_64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	set_cpu_cap(c, X86_FEATURE_SYSENTER32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	if (c->x86_power & (1 << 8)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 		set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 		set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) static void init_centaur(struct cpuinfo_x86 *c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #ifdef CONFIG_X86_32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	u32  fcr_set = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	u32  fcr_clr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	u32  lo, hi, newlo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	u32  aa, bb, cc, dd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	 * Bit 31 in normal CPUID used for nonstandard 3DNow ID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	 * 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	clear_cpu_cap(c, 0*32+31);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	early_init_centaur(c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	init_intel_cacheinfo(c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	detect_num_cpu_cores(c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #ifdef CONFIG_X86_32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	detect_ht(c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	if (c->cpuid_level > 9) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 		unsigned int eax = cpuid_eax(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 		 * Check for version and the number of counters
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 		 * Version(eax[7:0]) can't be 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 		 * Counters(eax[15:8]) should be greater than 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 		if ((eax & 0xff) && (((eax >> 8) & 0xff) > 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 			set_cpu_cap(c, X86_FEATURE_ARCH_PERFMON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #ifdef CONFIG_X86_32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	if (c->x86 == 5) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 		switch (c->x86_model) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 		case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 			name = "C6";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 			fcr_set = ECX8|DSMC|EDCTLB|EMMX|ERETSTK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 			fcr_clr = DPDC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 			pr_notice("Disabling bugged TSC.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 			clear_cpu_cap(c, X86_FEATURE_TSC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 		case 8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 			switch (c->x86_stepping) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 			default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 			name = "2";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 				break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 			case 7 ... 9:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 				name = "2A";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 				break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 			case 10 ... 15:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 				name = "2B";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 				break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 			}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 			fcr_set = ECX8|DSMC|DTLOCK|EMMX|EBRPRED|ERETSTK|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 				  E2MMX|EAMD3D;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 			fcr_clr = DPDC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 		case 9:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 			name = "3";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 			fcr_set = ECX8|DSMC|DTLOCK|EMMX|EBRPRED|ERETSTK|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 				  E2MMX|EAMD3D;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 			fcr_clr = DPDC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 		default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 			name = "??";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 		rdmsr(MSR_IDT_FCR1, lo, hi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 		newlo = (lo|fcr_set) & (~fcr_clr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 		if (newlo != lo) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 			pr_info("Centaur FCR was 0x%X now 0x%X\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 				lo, newlo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 			wrmsr(MSR_IDT_FCR1, newlo, hi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 		} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 			pr_info("Centaur FCR is 0x%X\n", lo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 		/* Emulate MTRRs using Centaur's MCR. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 		set_cpu_cap(c, X86_FEATURE_CENTAUR_MCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 		/* Report CX8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 		set_cpu_cap(c, X86_FEATURE_CX8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 		/* Set 3DNow! on Winchip 2 and above. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 		if (c->x86_model >= 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 			set_cpu_cap(c, X86_FEATURE_3DNOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 		/* See if we can find out some more. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 		if (cpuid_eax(0x80000000) >= 0x80000005) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 			/* Yes, we can. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 			cpuid(0x80000005, &aa, &bb, &cc, &dd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 			/* Add L1 data and code cache sizes. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 			c->x86_cache_size = (cc>>24)+(dd>>24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 		sprintf(c->x86_model_id, "WinChip %s", name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	if (c->x86 == 6 || c->x86 >= 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 		init_c3(c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #ifdef CONFIG_X86_64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	init_ia32_feat_ctl(c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #ifdef CONFIG_X86_32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) static unsigned int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) centaur_size_cache(struct cpuinfo_x86 *c, unsigned int size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	/* VIA C3 CPUs (670-68F) need further shifting. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	if ((c->x86 == 6) && ((c->x86_model == 7) || (c->x86_model == 8)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 		size >>= 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	 * There's also an erratum in Nehemiah stepping 1, which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	 * returns '65KB' instead of '64KB'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	 *  - Note, it seems this may only be in engineering samples.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	if ((c->x86 == 6) && (c->x86_model == 9) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 				(c->x86_stepping == 1) && (size == 65))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 		size -= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	return size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) static const struct cpu_dev centaur_cpu_dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	.c_vendor	= "Centaur",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	.c_ident	= { "CentaurHauls" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	.c_early_init	= early_init_centaur,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	.c_init		= init_centaur,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #ifdef CONFIG_X86_32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	.legacy_cache_size = centaur_size_cache,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	.c_x86_vendor	= X86_VENDOR_CENTAUR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) cpu_dev_register(centaur_cpu_dev);