^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) #include <linux/export.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) #include <linux/elf.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #include <linux/mm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/sched.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/sched/clock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/random.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/topology.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <asm/processor.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <asm/apic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <asm/cacheinfo.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <asm/cpu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <asm/spec-ctrl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <asm/smp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <asm/numa.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <asm/pci-direct.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <asm/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <asm/debugreg.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <asm/resctrl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #ifdef CONFIG_X86_64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) # include <asm/mmconfig.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) # include <asm/set_memory.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include "cpu.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) static const int amd_erratum_383[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) static const int amd_erratum_400[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) static const int amd_erratum_1054[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) static bool cpu_has_amd_erratum(struct cpuinfo_x86 *cpu, const int *erratum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * nodes_per_socket: Stores the number of nodes per socket.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * Refer to Fam15h Models 00-0fh BKDG - CPUID Fn8000_001E_ECX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * Node Identifiers[10:8]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) static u32 nodes_per_socket = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) static inline int rdmsrl_amd_safe(unsigned msr, unsigned long long *p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) u32 gprs[8] = { 0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) WARN_ONCE((boot_cpu_data.x86 != 0xf),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) "%s should only be used on K8!\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) gprs[1] = msr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) gprs[7] = 0x9c5a203a;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) err = rdmsr_safe_regs(gprs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) *p = gprs[0] | ((u64)gprs[2] << 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) static inline int wrmsrl_amd_safe(unsigned msr, unsigned long long val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) u32 gprs[8] = { 0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) WARN_ONCE((boot_cpu_data.x86 != 0xf),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) "%s should only be used on K8!\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) gprs[0] = (u32)val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) gprs[1] = msr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) gprs[2] = val >> 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) gprs[7] = 0x9c5a203a;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) return wrmsr_safe_regs(gprs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) * B step AMD K6 before B 9730xxxx have hardware bugs that can cause
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) * misexecution of code under Linux. Owners of such processors should
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) * contact AMD for precise details and a CPU swap.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) * See http://www.multimania.com/poulot/k6bug.html
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) * and section 2.6.2 of "AMD-K6 Processor Revision Guide - Model 6"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) * (Publication # 21266 Issue Date: August 1998)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) * The following test is erm.. interesting. AMD neglected to up
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) * the chip setting when fixing the bug but they also tweaked some
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) * performance at the same time..
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #ifdef CONFIG_X86_32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) extern __visible void vide(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) __asm__(".text\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) ".globl vide\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) ".type vide, @function\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) ".align 4\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) "vide: ret\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) static void init_amd_k5(struct cpuinfo_x86 *c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #ifdef CONFIG_X86_32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) * General Systems BIOSen alias the cpu frequency registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) * of the Elan at 0x000df000. Unfortunately, one of the Linux
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) * drivers subsequently pokes it, and changes the CPU speed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) * Workaround : Remove the unneeded alias.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define CBAR (0xfffc) /* Configuration Base Address (32-bit) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define CBAR_ENB (0x80000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define CBAR_KEY (0X000000CB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) if (c->x86_model == 9 || c->x86_model == 10) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) if (inl(CBAR) & CBAR_ENB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) outl(0 | CBAR_KEY, CBAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) static void init_amd_k6(struct cpuinfo_x86 *c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #ifdef CONFIG_X86_32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) u32 l, h;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) int mbytes = get_num_physpages() >> (20-PAGE_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) if (c->x86_model < 6) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) /* Based on AMD doc 20734R - June 2000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) if (c->x86_model == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) clear_cpu_cap(c, X86_FEATURE_APIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) set_cpu_cap(c, X86_FEATURE_PGE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) if (c->x86_model == 6 && c->x86_stepping == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) const int K6_BUG_LOOP = 1000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) int n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) void (*f_vide)(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) u64 d, d2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) pr_info("AMD K6 stepping B detected - ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) * It looks like AMD fixed the 2.6.2 bug and improved indirect
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) * calls at the same time.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) n = K6_BUG_LOOP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) f_vide = vide;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) OPTIMIZER_HIDE_VAR(f_vide);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) d = rdtsc();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) while (n--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) f_vide();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) d2 = rdtsc();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) d = d2-d;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) if (d > 20*K6_BUG_LOOP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) pr_cont("system stability may be impaired when more than 32 MB are used.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) pr_cont("probably OK (after B9730xxxx).\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) /* K6 with old style WHCR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) if (c->x86_model < 8 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) (c->x86_model == 8 && c->x86_stepping < 8)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) /* We can only write allocate on the low 508Mb */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) if (mbytes > 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) mbytes = 508;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) rdmsr(MSR_K6_WHCR, l, h);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) if ((l&0x0000FFFF) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) l = (1<<0)|((mbytes/4)<<1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) local_irq_save(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) wbinvd();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) wrmsr(MSR_K6_WHCR, l, h);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) local_irq_restore(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) pr_info("Enabling old style K6 write allocation for %d Mb\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) mbytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) if ((c->x86_model == 8 && c->x86_stepping > 7) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) c->x86_model == 9 || c->x86_model == 13) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) /* The more serious chips .. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) if (mbytes > 4092)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) mbytes = 4092;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) rdmsr(MSR_K6_WHCR, l, h);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) if ((l&0xFFFF0000) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) l = ((mbytes>>2)<<22)|(1<<16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) local_irq_save(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) wbinvd();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) wrmsr(MSR_K6_WHCR, l, h);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) local_irq_restore(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) pr_info("Enabling new style K6 write allocation for %d Mb\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) mbytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) if (c->x86_model == 10) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) /* AMD Geode LX is model 10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) /* placeholder for any needed mods */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) static void init_amd_k7(struct cpuinfo_x86 *c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #ifdef CONFIG_X86_32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) u32 l, h;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) * Bit 15 of Athlon specific MSR 15, needs to be 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) * to enable SSE on Palomino/Morgan/Barton CPU's.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) * If the BIOS didn't enable it already, enable it here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) if (c->x86_model >= 6 && c->x86_model <= 10) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) if (!cpu_has(c, X86_FEATURE_XMM)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) pr_info("Enabling disabled K7/SSE Support.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) msr_clear_bit(MSR_K7_HWCR, 15);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) set_cpu_cap(c, X86_FEATURE_XMM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) * It's been determined by AMD that Athlons since model 8 stepping 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) * are more robust with CLK_CTL set to 200xxxxx instead of 600xxxxx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) * As per AMD technical note 27212 0.2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) if ((c->x86_model == 8 && c->x86_stepping >= 1) || (c->x86_model > 8)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) rdmsr(MSR_K7_CLK_CTL, l, h);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) if ((l & 0xfff00000) != 0x20000000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) pr_info("CPU: CLK_CTL MSR was %x. Reprogramming to %x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) l, ((l & 0x000fffff)|0x20000000));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) wrmsr(MSR_K7_CLK_CTL, (l & 0x000fffff)|0x20000000, h);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) /* calling is from identify_secondary_cpu() ? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) if (!c->cpu_index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) * Certain Athlons might work (for various values of 'work') in SMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) * but they are not certified as MP capable.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) /* Athlon 660/661 is valid. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) if ((c->x86_model == 6) && ((c->x86_stepping == 0) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) (c->x86_stepping == 1)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) /* Duron 670 is valid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) if ((c->x86_model == 7) && (c->x86_stepping == 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) * Athlon 662, Duron 671, and Athlon >model 7 have capability
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) * bit. It's worth noting that the A5 stepping (662) of some
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) * Athlon XP's have the MP bit set.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) * See http://www.heise.de/newsticker/data/jow-18.10.01-000 for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) * more.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) if (((c->x86_model == 6) && (c->x86_stepping >= 2)) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) ((c->x86_model == 7) && (c->x86_stepping >= 1)) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) (c->x86_model > 7))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) if (cpu_has(c, X86_FEATURE_MP))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) /* If we get here, not a certified SMP capable AMD system. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) * Don't taint if we are running SMP kernel on a single non-MP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) * approved Athlon
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) WARN_ONCE(1, "WARNING: This combination of AMD"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) " processors is not suitable for SMP.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_NOW_UNRELIABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #ifdef CONFIG_NUMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) * To workaround broken NUMA config. Read the comment in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) * srat_detect_node().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) static int nearby_node(int apicid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) int i, node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) for (i = apicid - 1; i >= 0; i--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) node = __apicid_to_node[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) if (node != NUMA_NO_NODE && node_online(node))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) return node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) for (i = apicid + 1; i < MAX_LOCAL_APIC; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) node = __apicid_to_node[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) if (node != NUMA_NO_NODE && node_online(node))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) return node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) return first_node(node_online_map); /* Shouldn't happen */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) * Fix up cpu_core_id for pre-F17h systems to be in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) * [0 .. cores_per_node - 1] range. Not really needed but
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) * kept so as not to break existing setups.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) static void legacy_fixup_core_id(struct cpuinfo_x86 *c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) u32 cus_per_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) if (c->x86 >= 0x17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) cus_per_node = c->x86_max_cores / nodes_per_socket;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) c->cpu_core_id %= cus_per_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) * Fixup core topology information for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) * (1) AMD multi-node processors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) * Assumption: Number of cores in each internal node is the same.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) * (2) AMD processors supporting compute units
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) static void amd_get_topology(struct cpuinfo_x86 *c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) int cpu = smp_processor_id();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) /* get information required for multi-node processors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) if (boot_cpu_has(X86_FEATURE_TOPOEXT)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) u32 eax, ebx, ecx, edx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) cpuid(0x8000001e, &eax, &ebx, &ecx, &edx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) c->cpu_die_id = ecx & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) if (c->x86 == 0x15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) c->cu_id = ebx & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) if (c->x86 >= 0x17) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) c->cpu_core_id = ebx & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) if (smp_num_siblings > 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) c->x86_max_cores /= smp_num_siblings;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) * In case leaf B is available, use it to derive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) * topology information.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) err = detect_extended_topology(c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) if (!err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) c->x86_coreid_bits = get_count_order(c->x86_max_cores);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) cacheinfo_amd_init_llc_id(c, cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) } else if (cpu_has(c, X86_FEATURE_NODEID_MSR)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) u64 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) rdmsrl(MSR_FAM10H_NODE_ID, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) c->cpu_die_id = value & 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) per_cpu(cpu_llc_id, cpu) = c->cpu_die_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) if (nodes_per_socket > 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) set_cpu_cap(c, X86_FEATURE_AMD_DCM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) legacy_fixup_core_id(c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) * On a AMD dual core setup the lower bits of the APIC id distinguish the cores.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) * Assumes number of cores is a power of two.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) static void amd_detect_cmp(struct cpuinfo_x86 *c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) unsigned bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) int cpu = smp_processor_id();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) bits = c->x86_coreid_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) /* Low order bits define the core id (index of core in socket) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) c->cpu_core_id = c->initial_apicid & ((1 << bits)-1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) /* Convert the initial APIC ID into the socket ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) c->phys_proc_id = c->initial_apicid >> bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) /* use socket ID also for last level cache */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) per_cpu(cpu_llc_id, cpu) = c->cpu_die_id = c->phys_proc_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) static void amd_detect_ppin(struct cpuinfo_x86 *c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) unsigned long long val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) if (!cpu_has(c, X86_FEATURE_AMD_PPIN))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) /* When PPIN is defined in CPUID, still need to check PPIN_CTL MSR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) if (rdmsrl_safe(MSR_AMD_PPIN_CTL, &val))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) goto clear_ppin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) /* PPIN is locked in disabled mode, clear feature bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) if ((val & 3UL) == 1UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) goto clear_ppin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) /* If PPIN is disabled, try to enable it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) if (!(val & 2UL)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) wrmsrl_safe(MSR_AMD_PPIN_CTL, val | 2UL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) rdmsrl_safe(MSR_AMD_PPIN_CTL, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) /* If PPIN_EN bit is 1, return from here; otherwise fall through */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) if (val & 2UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) clear_ppin:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) clear_cpu_cap(c, X86_FEATURE_AMD_PPIN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) u16 amd_get_nb_id(int cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) return per_cpu(cpu_llc_id, cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) EXPORT_SYMBOL_GPL(amd_get_nb_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) u32 amd_get_nodes_per_socket(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) return nodes_per_socket;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) EXPORT_SYMBOL_GPL(amd_get_nodes_per_socket);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) static void srat_detect_node(struct cpuinfo_x86 *c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) #ifdef CONFIG_NUMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) int cpu = smp_processor_id();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) int node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) unsigned apicid = c->apicid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) node = numa_cpu_node(cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) if (node == NUMA_NO_NODE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) node = per_cpu(cpu_llc_id, cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) * On multi-fabric platform (e.g. Numascale NumaChip) a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) * platform-specific handler needs to be called to fixup some
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) * IDs of the CPU.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) if (x86_cpuinit.fixup_cpu_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) x86_cpuinit.fixup_cpu_id(c, node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) if (!node_online(node)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) * Two possibilities here:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) * - The CPU is missing memory and no node was created. In
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) * that case try picking one from a nearby CPU.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) * - The APIC IDs differ from the HyperTransport node IDs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) * which the K8 northbridge parsing fills in. Assume
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) * they are all increased by a constant offset, but in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) * the same order as the HT nodeids. If that doesn't
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) * result in a usable node fall back to the path for the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) * previous case.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) * This workaround operates directly on the mapping between
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) * APIC ID and NUMA node, assuming certain relationship
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) * between APIC ID, HT node ID and NUMA topology. As going
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) * through CPU mapping may alter the outcome, directly
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) * access __apicid_to_node[].
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) int ht_nodeid = c->initial_apicid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) if (__apicid_to_node[ht_nodeid] != NUMA_NO_NODE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) node = __apicid_to_node[ht_nodeid];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) /* Pick a nearby node */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) if (!node_online(node))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) node = nearby_node(apicid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) numa_set_node(cpu, node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) static void early_init_amd_mc(struct cpuinfo_x86 *c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) #ifdef CONFIG_SMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) unsigned bits, ecx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) /* Multi core CPU? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) if (c->extended_cpuid_level < 0x80000008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) ecx = cpuid_ecx(0x80000008);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) c->x86_max_cores = (ecx & 0xff) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) /* CPU telling us the core id bits shift? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) bits = (ecx >> 12) & 0xF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) /* Otherwise recompute */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) if (bits == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) while ((1 << bits) < c->x86_max_cores)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) bits++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) c->x86_coreid_bits = bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) static void bsp_init_amd(struct cpuinfo_x86 *c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) #ifdef CONFIG_X86_64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) if (c->x86 >= 0xf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) unsigned long long tseg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) * Split up direct mapping around the TSEG SMM area.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) * Don't do it for gbpages because there seems very little
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) * benefit in doing so.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) if (!rdmsrl_safe(MSR_K8_TSEG_ADDR, &tseg)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) unsigned long pfn = tseg >> PAGE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) pr_debug("tseg: %010llx\n", tseg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) if (pfn_range_is_mapped(pfn, pfn + 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) set_memory_4k((unsigned long)__va(tseg), 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) if (cpu_has(c, X86_FEATURE_CONSTANT_TSC)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) if (c->x86 > 0x10 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) (c->x86 == 0x10 && c->x86_model >= 0x2)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) u64 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) rdmsrl(MSR_K7_HWCR, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) if (!(val & BIT(24)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) pr_warn(FW_BUG "TSC doesn't count with P0 frequency!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) if (c->x86 == 0x15) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) unsigned long upperbit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) u32 cpuid, assoc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) cpuid = cpuid_edx(0x80000005);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) assoc = cpuid >> 16 & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) upperbit = ((cpuid >> 24) << 10) / assoc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) va_align.mask = (upperbit - 1) & PAGE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) va_align.flags = ALIGN_VA_32 | ALIGN_VA_64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) /* A random value per boot for bit slice [12:upper_bit) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) va_align.bits = get_random_int() & va_align.mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) if (cpu_has(c, X86_FEATURE_MWAITX))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) use_mwaitx_delay();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) if (boot_cpu_has(X86_FEATURE_TOPOEXT)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) u32 ecx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) ecx = cpuid_ecx(0x8000001e);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) __max_die_per_package = nodes_per_socket = ((ecx >> 8) & 7) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) } else if (boot_cpu_has(X86_FEATURE_NODEID_MSR)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) u64 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) rdmsrl(MSR_FAM10H_NODE_ID, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) __max_die_per_package = nodes_per_socket = ((value >> 3) & 7) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) if (!boot_cpu_has(X86_FEATURE_AMD_SSBD) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) !boot_cpu_has(X86_FEATURE_VIRT_SSBD) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) c->x86 >= 0x15 && c->x86 <= 0x17) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) unsigned int bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) switch (c->x86) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) case 0x15: bit = 54; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) case 0x16: bit = 33; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) case 0x17: bit = 10; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) default: return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) * Try to cache the base value so further operations can
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) * avoid RMW. If that faults, do not enable SSBD.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) if (!rdmsrl_safe(MSR_AMD64_LS_CFG, &x86_amd_ls_cfg_base)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) setup_force_cpu_cap(X86_FEATURE_LS_CFG_SSBD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) setup_force_cpu_cap(X86_FEATURE_SSBD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) x86_amd_ls_cfg_ssbd_mask = 1ULL << bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) resctrl_cpu_detect(c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) static void early_detect_mem_encrypt(struct cpuinfo_x86 *c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) u64 msr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) * BIOS support is required for SME and SEV.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) * For SME: If BIOS has enabled SME then adjust x86_phys_bits by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) * the SME physical address space reduction value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) * If BIOS has not enabled SME then don't advertise the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) * SME feature (set in scattered.c).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) * For SEV: If BIOS has not enabled SEV then don't advertise the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) * SEV and SEV_ES feature (set in scattered.c).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) * In all cases, since support for SME and SEV requires long mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) * don't advertise the feature under CONFIG_X86_32.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) if (cpu_has(c, X86_FEATURE_SME) || cpu_has(c, X86_FEATURE_SEV)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) /* Check if memory encryption is enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) rdmsrl(MSR_K8_SYSCFG, msr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) if (!(msr & MSR_K8_SYSCFG_MEM_ENCRYPT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) goto clear_all;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) * Always adjust physical address bits. Even though this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) * will be a value above 32-bits this is still done for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) * CONFIG_X86_32 so that accurate values are reported.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) c->x86_phys_bits -= (cpuid_ebx(0x8000001f) >> 6) & 0x3f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) if (IS_ENABLED(CONFIG_X86_32))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) goto clear_all;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) rdmsrl(MSR_K7_HWCR, msr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) if (!(msr & MSR_K7_HWCR_SMMLOCK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) goto clear_sev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) clear_all:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) setup_clear_cpu_cap(X86_FEATURE_SME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) clear_sev:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) setup_clear_cpu_cap(X86_FEATURE_SEV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) setup_clear_cpu_cap(X86_FEATURE_SEV_ES);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) static void early_init_amd(struct cpuinfo_x86 *c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) u64 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) u32 dummy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) early_init_amd_mc(c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) #ifdef CONFIG_X86_32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) if (c->x86 == 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) set_cpu_cap(c, X86_FEATURE_K7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) if (c->x86 >= 0xf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) set_cpu_cap(c, X86_FEATURE_K8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) rdmsr_safe(MSR_AMD64_PATCH_LEVEL, &c->microcode, &dummy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) * with P/T states and does not stop in deep C-states
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) if (c->x86_power & (1 << 8)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) /* Bit 12 of 8000_0007 edx is accumulated power mechanism. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) if (c->x86_power & BIT(12))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) set_cpu_cap(c, X86_FEATURE_ACC_POWER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) #ifdef CONFIG_X86_64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) set_cpu_cap(c, X86_FEATURE_SYSCALL32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) /* Set MTRR capability flag if appropriate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) if (c->x86 == 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) if (c->x86_model == 13 || c->x86_model == 9 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) (c->x86_model == 8 && c->x86_stepping >= 8))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) set_cpu_cap(c, X86_FEATURE_K6_MTRR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) #if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_PCI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) * ApicID can always be treated as an 8-bit value for AMD APIC versions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) * >= 0x10, but even old K8s came out of reset with version 0x10. So, we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) * can safely set X86_FEATURE_EXTD_APICID unconditionally for families
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) * after 16h.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) if (boot_cpu_has(X86_FEATURE_APIC)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) if (c->x86 > 0x16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) set_cpu_cap(c, X86_FEATURE_EXTD_APICID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) else if (c->x86 >= 0xf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) /* check CPU config space for extended APIC ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) val = read_pci_config(0, 24, 0, 0x68);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) if ((val >> 17 & 0x3) == 0x3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) set_cpu_cap(c, X86_FEATURE_EXTD_APICID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) * This is only needed to tell the kernel whether to use VMCALL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) * and VMMCALL. VMMCALL is never executed except under virt, so
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) * we can set it unconditionally.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) set_cpu_cap(c, X86_FEATURE_VMMCALL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) /* F16h erratum 793, CVE-2013-6885 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) if (c->x86 == 0x16 && c->x86_model <= 0xf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) msr_set_bit(MSR_AMD64_LS_CFG, 15);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) * Check whether the machine is affected by erratum 400. This is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) * used to select the proper idle routine and to enable the check
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) * whether the machine is affected in arch_post_acpi_init(), which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) * sets the X86_BUG_AMD_APIC_C1E bug depending on the MSR check.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) if (cpu_has_amd_erratum(c, amd_erratum_400))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) set_cpu_bug(c, X86_BUG_AMD_E400);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) early_detect_mem_encrypt(c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) /* Re-enable TopologyExtensions if switched off by BIOS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) if (c->x86 == 0x15 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) (c->x86_model >= 0x10 && c->x86_model <= 0x6f) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) !cpu_has(c, X86_FEATURE_TOPOEXT)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) if (msr_set_bit(0xc0011005, 54) > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) rdmsrl(0xc0011005, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) if (value & BIT_64(54)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) set_cpu_cap(c, X86_FEATURE_TOPOEXT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) pr_info_once(FW_INFO "CPU: Re-enabling disabled Topology Extensions Support.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) if (cpu_has(c, X86_FEATURE_TOPOEXT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) smp_num_siblings = ((cpuid_ebx(0x8000001e) >> 8) & 0xff) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) static void init_amd_k8(struct cpuinfo_x86 *c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) u32 level;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) u64 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) /* On C+ stepping K8 rep microcode works well for copy/memset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) level = cpuid_eax(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) if ((level >= 0x0f48 && level < 0x0f50) || level >= 0x0f58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) set_cpu_cap(c, X86_FEATURE_REP_GOOD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) * Some BIOSes incorrectly force this feature, but only K8 revision D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) * (model = 0x14) and later actually support it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) * (AMD Erratum #110, docId: 25759).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) if (c->x86_model < 0x14 && cpu_has(c, X86_FEATURE_LAHF_LM)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) clear_cpu_cap(c, X86_FEATURE_LAHF_LM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) if (!rdmsrl_amd_safe(0xc001100d, &value)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) value &= ~BIT_64(32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) wrmsrl_amd_safe(0xc001100d, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) if (!c->x86_model_id[0])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) strcpy(c->x86_model_id, "Hammer");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) #ifdef CONFIG_SMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) * Disable TLB flush filter by setting HWCR.FFDIS on K8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) * bit 6 of msr C001_0015
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) * Errata 63 for SH-B3 steppings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) * Errata 122 for all steppings (F+ have it disabled by default)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) msr_set_bit(MSR_K7_HWCR, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) set_cpu_bug(c, X86_BUG_SWAPGS_FENCE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) static void init_amd_gh(struct cpuinfo_x86 *c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) #ifdef CONFIG_MMCONF_FAM10H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) /* do this for boot cpu */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) if (c == &boot_cpu_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) check_enable_amd_mmconf_dmi();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) fam10h_check_enable_mmcfg();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) * Disable GART TLB Walk Errors on Fam10h. We do this here because this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) * is always needed when GART is enabled, even in a kernel which has no
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) * MCE support built in. BIOS should disable GartTlbWlk Errors already.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) * If it doesn't, we do it here as suggested by the BKDG.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) * Fixes: https://bugzilla.kernel.org/show_bug.cgi?id=33012
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) msr_set_bit(MSR_AMD64_MCx_MASK(4), 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) * On family 10h BIOS may not have properly enabled WC+ support, causing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) * it to be converted to CD memtype. This may result in performance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) * degradation for certain nested-paging guests. Prevent this conversion
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) * by clearing bit 24 in MSR_AMD64_BU_CFG2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) * NOTE: we want to use the _safe accessors so as not to #GP kvm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) * guests on older kvm hosts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) msr_clear_bit(MSR_AMD64_BU_CFG2, 24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) if (cpu_has_amd_erratum(c, amd_erratum_383))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) set_cpu_bug(c, X86_BUG_AMD_TLB_MMATCH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) #define MSR_AMD64_DE_CFG 0xC0011029
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) static void init_amd_ln(struct cpuinfo_x86 *c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) * Apply erratum 665 fix unconditionally so machines without a BIOS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) * fix work.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) msr_set_bit(MSR_AMD64_DE_CFG, 31);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) static bool rdrand_force;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) static int __init rdrand_cmdline(char *str)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) if (!str)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) if (!strcmp(str, "force"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) rdrand_force = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) early_param("rdrand", rdrand_cmdline);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) static void clear_rdrand_cpuid_bit(struct cpuinfo_x86 *c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) * Saving of the MSR used to hide the RDRAND support during
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) * suspend/resume is done by arch/x86/power/cpu.c, which is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) * dependent on CONFIG_PM_SLEEP.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) if (!IS_ENABLED(CONFIG_PM_SLEEP))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) * The nordrand option can clear X86_FEATURE_RDRAND, so check for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) * RDRAND support using the CPUID function directly.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) if (!(cpuid_ecx(1) & BIT(30)) || rdrand_force)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) msr_clear_bit(MSR_AMD64_CPUID_FN_1, 62);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) * Verify that the CPUID change has occurred in case the kernel is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) * running virtualized and the hypervisor doesn't support the MSR.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) if (cpuid_ecx(1) & BIT(30)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) pr_info_once("BIOS may not properly restore RDRAND after suspend, but hypervisor does not support hiding RDRAND via CPUID.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) clear_cpu_cap(c, X86_FEATURE_RDRAND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) pr_info_once("BIOS may not properly restore RDRAND after suspend, hiding RDRAND via CPUID. Use rdrand=force to reenable.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) static void init_amd_jg(struct cpuinfo_x86 *c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) * Some BIOS implementations do not restore proper RDRAND support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) * across suspend and resume. Check on whether to hide the RDRAND
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) * instruction support via CPUID.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) clear_rdrand_cpuid_bit(c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) static void init_amd_bd(struct cpuinfo_x86 *c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) u64 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) * The way access filter has a performance penalty on some workloads.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) * Disable it on the affected CPUs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) if ((c->x86_model >= 0x02) && (c->x86_model < 0x20)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) if (!rdmsrl_safe(MSR_F15H_IC_CFG, &value) && !(value & 0x1E)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) value |= 0x1E;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) wrmsrl_safe(MSR_F15H_IC_CFG, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) * Some BIOS implementations do not restore proper RDRAND support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) * across suspend and resume. Check on whether to hide the RDRAND
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) * instruction support via CPUID.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) clear_rdrand_cpuid_bit(c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) static void init_amd_zn(struct cpuinfo_x86 *c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) set_cpu_cap(c, X86_FEATURE_ZEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) #ifdef CONFIG_NUMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) node_reclaim_distance = 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) * Fix erratum 1076: CPB feature bit not being set in CPUID.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) * Always set it, except when running under a hypervisor.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) if (!cpu_has(c, X86_FEATURE_HYPERVISOR) && !cpu_has(c, X86_FEATURE_CPB))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) set_cpu_cap(c, X86_FEATURE_CPB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) static void init_amd(struct cpuinfo_x86 *c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) early_init_amd(c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) * Bit 31 in normal CPUID used for nonstandard 3DNow ID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) * 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) clear_cpu_cap(c, 0*32+31);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) if (c->x86 >= 0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) set_cpu_cap(c, X86_FEATURE_REP_GOOD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) /* get apicid instead of initial apic id from cpuid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) c->apicid = hard_smp_processor_id();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) /* K6s reports MCEs but don't actually have all the MSRs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) if (c->x86 < 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) clear_cpu_cap(c, X86_FEATURE_MCE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) switch (c->x86) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) case 4: init_amd_k5(c); break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) case 5: init_amd_k6(c); break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) case 6: init_amd_k7(c); break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) case 0xf: init_amd_k8(c); break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) case 0x10: init_amd_gh(c); break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) case 0x12: init_amd_ln(c); break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) case 0x15: init_amd_bd(c); break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) case 0x16: init_amd_jg(c); break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) case 0x17: fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) case 0x19: init_amd_zn(c); break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) * Enable workaround for FXSAVE leak on CPUs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) * without a XSaveErPtr feature
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) if ((c->x86 >= 6) && (!cpu_has(c, X86_FEATURE_XSAVEERPTR)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) set_cpu_bug(c, X86_BUG_FXSAVE_LEAK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) cpu_detect_cache_sizes(c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) amd_detect_cmp(c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) amd_get_topology(c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) srat_detect_node(c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) amd_detect_ppin(c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) init_amd_cacheinfo(c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) if (cpu_has(c, X86_FEATURE_XMM2)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) * Use LFENCE for execution serialization. On families which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) * don't have that MSR, LFENCE is already serializing.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) * msr_set_bit() uses the safe accessors, too, even if the MSR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) * is not present.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) msr_set_bit(MSR_F10H_DECFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) MSR_F10H_DECFG_LFENCE_SERIALIZE_BIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) /* A serializing LFENCE stops RDTSC speculation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) * Family 0x12 and above processors have APIC timer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) * running in deep C states.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) if (c->x86 > 0x11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) set_cpu_cap(c, X86_FEATURE_ARAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) /* 3DNow or LM implies PREFETCHW */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) if (!cpu_has(c, X86_FEATURE_3DNOWPREFETCH))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) if (cpu_has(c, X86_FEATURE_3DNOW) || cpu_has(c, X86_FEATURE_LM))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) set_cpu_cap(c, X86_FEATURE_3DNOWPREFETCH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) /* AMD CPUs don't reset SS attributes on SYSRET, Xen does. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) if (!cpu_has(c, X86_FEATURE_XENPV))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) set_cpu_bug(c, X86_BUG_SYSRET_SS_ATTRS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) * Turn on the Instructions Retired free counter on machines not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) * susceptible to erratum #1054 "Instructions Retired Performance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) * Counter May Be Inaccurate".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) if (cpu_has(c, X86_FEATURE_IRPERF) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) !cpu_has_amd_erratum(c, amd_erratum_1054))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) msr_set_bit(MSR_K7_HWCR, MSR_K7_HWCR_IRPERF_EN_BIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) check_null_seg_clears_base(c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) #ifdef CONFIG_X86_32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) static unsigned int amd_size_cache(struct cpuinfo_x86 *c, unsigned int size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) /* AMD errata T13 (order #21922) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) if (c->x86 == 6) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) /* Duron Rev A0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) if (c->x86_model == 3 && c->x86_stepping == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) size = 64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) /* Tbird rev A1/A2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) if (c->x86_model == 4 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) (c->x86_stepping == 0 || c->x86_stepping == 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) size = 256;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) return size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) static void cpu_detect_tlb_amd(struct cpuinfo_x86 *c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) u32 ebx, eax, ecx, edx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) u16 mask = 0xfff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) if (c->x86 < 0xf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) if (c->extended_cpuid_level < 0x80000006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) cpuid(0x80000006, &eax, &ebx, &ecx, &edx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) tlb_lld_4k[ENTRIES] = (ebx >> 16) & mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) tlb_lli_4k[ENTRIES] = ebx & mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) * K8 doesn't have 2M/4M entries in the L2 TLB so read out the L1 TLB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) * characteristics from the CPUID function 0x80000005 instead.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) if (c->x86 == 0xf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) cpuid(0x80000005, &eax, &ebx, &ecx, &edx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) mask = 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) /* Handle DTLB 2M and 4M sizes, fall back to L1 if L2 is disabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) if (!((eax >> 16) & mask))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) tlb_lld_2m[ENTRIES] = (cpuid_eax(0x80000005) >> 16) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) tlb_lld_2m[ENTRIES] = (eax >> 16) & mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) /* a 4M entry uses two 2M entries */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) tlb_lld_4m[ENTRIES] = tlb_lld_2m[ENTRIES] >> 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) /* Handle ITLB 2M and 4M sizes, fall back to L1 if L2 is disabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) if (!(eax & mask)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) /* Erratum 658 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) if (c->x86 == 0x15 && c->x86_model <= 0x1f) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) tlb_lli_2m[ENTRIES] = 1024;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) cpuid(0x80000005, &eax, &ebx, &ecx, &edx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) tlb_lli_2m[ENTRIES] = eax & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) tlb_lli_2m[ENTRIES] = eax & mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) tlb_lli_4m[ENTRIES] = tlb_lli_2m[ENTRIES] >> 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) static const struct cpu_dev amd_cpu_dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) .c_vendor = "AMD",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) .c_ident = { "AuthenticAMD" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) #ifdef CONFIG_X86_32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) .legacy_models = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) { .family = 4, .model_names =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) [3] = "486 DX/2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) [7] = "486 DX/2-WB",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) [8] = "486 DX/4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) [9] = "486 DX/4-WB",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) [14] = "Am5x86-WT",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) [15] = "Am5x86-WB"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) .legacy_cache_size = amd_size_cache,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) .c_early_init = early_init_amd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) .c_detect_tlb = cpu_detect_tlb_amd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) .c_bsp_init = bsp_init_amd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) .c_init = init_amd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) .c_x86_vendor = X86_VENDOR_AMD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) cpu_dev_register(amd_cpu_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) * AMD errata checking
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) * Errata are defined as arrays of ints using the AMD_LEGACY_ERRATUM() or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) * AMD_OSVW_ERRATUM() macros. The latter is intended for newer errata that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) * have an OSVW id assigned, which it takes as first argument. Both take a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) * variable number of family-specific model-stepping ranges created by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) * AMD_MODEL_RANGE().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) * Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) * const int amd_erratum_319[] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) * AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0x4, 0x2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) * AMD_MODEL_RANGE(0x10, 0x8, 0x0, 0x8, 0x0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) * AMD_MODEL_RANGE(0x10, 0x9, 0x0, 0x9, 0x0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) #define AMD_LEGACY_ERRATUM(...) { -1, __VA_ARGS__, 0 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) #define AMD_OSVW_ERRATUM(osvw_id, ...) { osvw_id, __VA_ARGS__, 0 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) #define AMD_MODEL_RANGE(f, m_start, s_start, m_end, s_end) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) ((f << 24) | (m_start << 16) | (s_start << 12) | (m_end << 4) | (s_end))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) #define AMD_MODEL_RANGE_FAMILY(range) (((range) >> 24) & 0xff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) #define AMD_MODEL_RANGE_START(range) (((range) >> 12) & 0xfff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) #define AMD_MODEL_RANGE_END(range) ((range) & 0xfff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) static const int amd_erratum_400[] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) AMD_OSVW_ERRATUM(1, AMD_MODEL_RANGE(0xf, 0x41, 0x2, 0xff, 0xf),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0xff, 0xf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) static const int amd_erratum_383[] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) AMD_OSVW_ERRATUM(3, AMD_MODEL_RANGE(0x10, 0, 0, 0xff, 0xf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) /* #1054: Instructions Retired Performance Counter May Be Inaccurate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) static const int amd_erratum_1054[] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x17, 0, 0, 0x2f, 0xf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) static bool cpu_has_amd_erratum(struct cpuinfo_x86 *cpu, const int *erratum)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) int osvw_id = *erratum++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) u32 range;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) u32 ms;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) if (osvw_id >= 0 && osvw_id < 65536 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) cpu_has(cpu, X86_FEATURE_OSVW)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) u64 osvw_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) rdmsrl(MSR_AMD64_OSVW_ID_LENGTH, osvw_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) if (osvw_id < osvw_len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) u64 osvw_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) rdmsrl(MSR_AMD64_OSVW_STATUS + (osvw_id >> 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) osvw_bits);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) return osvw_bits & (1ULL << (osvw_id & 0x3f));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) /* OSVW unavailable or ID unknown, match family-model-stepping range */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) ms = (cpu->x86_model << 4) | cpu->x86_stepping;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) while ((range = *erratum++))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) if ((cpu->x86 == AMD_MODEL_RANGE_FAMILY(range)) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) (ms >= AMD_MODEL_RANGE_START(range)) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) (ms <= AMD_MODEL_RANGE_END(range)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) void set_dr_addr_mask(unsigned long mask, int dr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) if (!boot_cpu_has(X86_FEATURE_BPEXT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) switch (dr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) wrmsr(MSR_F16H_DR0_ADDR_MASK, mask, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) wrmsr(MSR_F16H_DR1_ADDR_MASK - 1 + dr, mask, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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