^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Firmware replacement code.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Work around broken BIOSes that don't set an aperture, only set the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * aperture in the AGP bridge, or set too small aperture.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * If all fails map the aperture over some low memory. This is cheaper than
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * doing bounce buffering. The memory is lost. This is done at early boot
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * because only the bootmem allocator can allocate 32+MB.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * Copyright 2002 Andi Kleen, SuSE Labs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define pr_fmt(fmt) "AGP: " fmt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/kcore.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/memblock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/mmzone.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/pci_ids.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/suspend.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <asm/e820/api.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <asm/iommu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <asm/gart.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <asm/pci-direct.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <asm/dma.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <asm/amd_nb.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <asm/x86_init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <linux/crash_dump.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * Using 512M as goal, in case kexec will load kernel_big
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * that will do the on-position decompress, and could overlap with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * with the gart aperture that is used.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * Sequence:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * kernel_small
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * ==> kexec (with kdump trigger path or gart still enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * ==> kernel_small (gart area become e820_reserved)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * ==> kexec (with kdump trigger path or gart still enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * ==> kerne_big (uncompressed size will be big than 64M or 128M)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * So don't use 512M below as gart iommu, leave the space for kernel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * code for safe.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define GART_MIN_ADDR (512ULL << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define GART_MAX_ADDR (1ULL << 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) int gart_iommu_aperture;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) int gart_iommu_aperture_disabled __initdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) int gart_iommu_aperture_allowed __initdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) int fallback_aper_order __initdata = 1; /* 64MB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) int fallback_aper_force __initdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) int fix_aperture __initdata = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #if defined(CONFIG_PROC_VMCORE) || defined(CONFIG_PROC_KCORE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) * If the first kernel maps the aperture over e820 RAM, the kdump kernel will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * use the same range because it will remain configured in the northbridge.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * Trying to dump this area via /proc/vmcore may crash the machine, so exclude
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) * it from vmcore.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) static unsigned long aperture_pfn_start, aperture_page_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) static int gart_mem_pfn_is_ram(unsigned long pfn)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) return likely((pfn < aperture_pfn_start) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) (pfn >= aperture_pfn_start + aperture_page_count));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) static void __init exclude_from_core(u64 aper_base, u32 aper_order)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) aperture_pfn_start = aper_base >> PAGE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) aperture_page_count = (32 * 1024 * 1024) << aper_order >> PAGE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #ifdef CONFIG_PROC_VMCORE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) WARN_ON(register_oldmem_pfn_is_ram(&gart_mem_pfn_is_ram));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #ifdef CONFIG_PROC_KCORE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) WARN_ON(register_mem_pfn_is_ram(&gart_mem_pfn_is_ram));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) static void exclude_from_core(u64 aper_base, u32 aper_order)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) /* This code runs before the PCI subsystem is initialized, so just
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) access the northbridge directly. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) static u32 __init allocate_aperture(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) u32 aper_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) unsigned long addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) /* aper_size should <= 1G */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) if (fallback_aper_order > 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) fallback_aper_order = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) aper_size = (32 * 1024 * 1024) << fallback_aper_order;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) * Aperture has to be naturally aligned. This means a 2GB aperture
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) * won't have much chance of finding a place in the lower 4GB of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) * memory. Unfortunately we cannot move it up because that would
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) * make the IOMMU useless.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) addr = memblock_find_in_range(GART_MIN_ADDR, GART_MAX_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) aper_size, aper_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) if (!addr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) pr_err("Cannot allocate aperture memory hole [mem %#010lx-%#010lx] (%uKB)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) addr, addr + aper_size - 1, aper_size >> 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) memblock_reserve(addr, aper_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) pr_info("Mapping aperture over RAM [mem %#010lx-%#010lx] (%uKB)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) addr, addr + aper_size - 1, aper_size >> 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) register_nosave_region(addr >> PAGE_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) (addr+aper_size) >> PAGE_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) return (u32)addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) /* Find a PCI capability */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) static u32 __init find_cap(int bus, int slot, int func, int cap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) int bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) u8 pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) if (!(read_pci_config_16(bus, slot, func, PCI_STATUS) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) PCI_STATUS_CAP_LIST))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) pos = read_pci_config_byte(bus, slot, func, PCI_CAPABILITY_LIST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) for (bytes = 0; bytes < 48 && pos >= 0x40; bytes++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) u8 id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) pos &= ~3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) id = read_pci_config_byte(bus, slot, func, pos+PCI_CAP_LIST_ID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) if (id == 0xff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) if (id == cap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) return pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) pos = read_pci_config_byte(bus, slot, func,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) pos+PCI_CAP_LIST_NEXT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) /* Read a standard AGPv3 bridge header */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) static u32 __init read_agp(int bus, int slot, int func, int cap, u32 *order)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) u32 apsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) u32 apsizereg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) int nbits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) u32 aper_low, aper_hi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) u64 aper;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) u32 old_order;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) pr_info("pci 0000:%02x:%02x:%02x: AGP bridge\n", bus, slot, func);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) apsizereg = read_pci_config_16(bus, slot, func, cap + 0x14);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) if (apsizereg == 0xffffffff) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) pr_err("pci 0000:%02x:%02x.%d: APSIZE unreadable\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) bus, slot, func);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) /* old_order could be the value from NB gart setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) old_order = *order;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) apsize = apsizereg & 0xfff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) /* Some BIOS use weird encodings not in the AGPv3 table. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) if (apsize & 0xff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) apsize |= 0xf00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) nbits = hweight16(apsize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) *order = 7 - nbits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) if ((int)*order < 0) /* < 32MB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) *order = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) aper_low = read_pci_config(bus, slot, func, 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) aper_hi = read_pci_config(bus, slot, func, 0x14);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) aper = (aper_low & ~((1<<22)-1)) | ((u64)aper_hi << 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) * On some sick chips, APSIZE is 0. It means it wants 4G
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) * so let double check that order, and lets trust AMD NB settings:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) pr_info("pci 0000:%02x:%02x.%d: AGP aperture [bus addr %#010Lx-%#010Lx] (old size %uMB)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) bus, slot, func, aper, aper + (32ULL << (old_order + 20)) - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 32 << old_order);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) if (aper + (32ULL<<(20 + *order)) > 0x100000000ULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) pr_info("pci 0000:%02x:%02x.%d: AGP aperture size %uMB (APSIZE %#x) is not right, using settings from NB\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) bus, slot, func, 32 << *order, apsizereg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) *order = old_order;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) pr_info("pci 0000:%02x:%02x.%d: AGP aperture [bus addr %#010Lx-%#010Lx] (%uMB, APSIZE %#x)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) bus, slot, func, aper, aper + (32ULL << (*order + 20)) - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 32 << *order, apsizereg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) if (!aperture_valid(aper, (32*1024*1024) << *order, 32<<20))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) return (u32)aper;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) * Look for an AGP bridge. Windows only expects the aperture in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) * AGP bridge and some BIOS forget to initialize the Northbridge too.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) * Work around this here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) * Do an PCI bus scan by hand because we're running before the PCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) * subsystem.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) * All AMD AGP bridges are AGPv3 compliant, so we can do this scan
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) * generically. It's probably overkill to always scan all slots because
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) * the AGP bridges should be always an own bus on the HT hierarchy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) * but do it here for future safety.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) static u32 __init search_agp_bridge(u32 *order, int *valid_agp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) int bus, slot, func;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) /* Poor man's PCI discovery */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) for (bus = 0; bus < 256; bus++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) for (slot = 0; slot < 32; slot++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) for (func = 0; func < 8; func++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) u32 class, cap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) u8 type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) class = read_pci_config(bus, slot, func,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) PCI_CLASS_REVISION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) if (class == 0xffffffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) switch (class >> 16) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) case PCI_CLASS_BRIDGE_HOST:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) case PCI_CLASS_BRIDGE_OTHER: /* needed? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) /* AGP bridge? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) cap = find_cap(bus, slot, func,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) PCI_CAP_ID_AGP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) if (!cap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) *valid_agp = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) return read_agp(bus, slot, func, cap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) order);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) /* No multi-function device? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) type = read_pci_config_byte(bus, slot, func,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) PCI_HEADER_TYPE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) if (!(type & 0x80))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) pr_info("No AGP bridge found\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) static bool gart_fix_e820 __initdata = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) static int __init parse_gart_mem(char *p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) return kstrtobool(p, &gart_fix_e820);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) early_param("gart_fix_e820", parse_gart_mem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) * With kexec/kdump, if the first kernel doesn't shut down the GART and the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) * second kernel allocates a different GART region, there might be two
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) * overlapping GART regions present:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) * - the first still used by the GART initialized in the first kernel.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) * - (sub-)set of it used as normal RAM by the second kernel.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) * which leads to memory corruptions and a kernel panic eventually.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) * This can also happen if the BIOS has forgotten to mark the GART region
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) * as reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) * Try to update the e820 map to mark that new region as reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) void __init early_gart_iommu_check(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) u32 agp_aper_order = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) int i, fix, slot, valid_agp = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) u32 ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) u32 aper_size = 0, aper_order = 0, last_aper_order = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) u64 aper_base = 0, last_aper_base = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) int aper_enabled = 0, last_aper_enabled = 0, last_valid = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) if (!amd_gart_present())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) if (!early_pci_allowed())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) /* This is mostly duplicate of iommu_hole_init */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) search_agp_bridge(&agp_aper_order, &valid_agp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) fix = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) for (i = 0; amd_nb_bus_dev_ranges[i].dev_limit; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) int bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) int dev_base, dev_limit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) bus = amd_nb_bus_dev_ranges[i].bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) dev_base = amd_nb_bus_dev_ranges[i].dev_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) dev_limit = amd_nb_bus_dev_ranges[i].dev_limit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) for (slot = dev_base; slot < dev_limit; slot++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) if (!early_is_amd_nb(read_pci_config(bus, slot, 3, 0x00)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) ctl = read_pci_config(bus, slot, 3, AMD64_GARTAPERTURECTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) aper_enabled = ctl & GARTEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) aper_order = (ctl >> 1) & 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) aper_size = (32 * 1024 * 1024) << aper_order;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) aper_base = read_pci_config(bus, slot, 3, AMD64_GARTAPERTUREBASE) & 0x7fff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) aper_base <<= 25;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) if (last_valid) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) if ((aper_order != last_aper_order) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) (aper_base != last_aper_base) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) (aper_enabled != last_aper_enabled)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) fix = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) last_aper_order = aper_order;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) last_aper_base = aper_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) last_aper_enabled = aper_enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) last_valid = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) if (!fix && !aper_enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) if (!aper_base || !aper_size || aper_base + aper_size > 0x100000000UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) fix = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) if (gart_fix_e820 && !fix && aper_enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) if (e820__mapped_any(aper_base, aper_base + aper_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) E820_TYPE_RAM)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) /* reserve it, so we can reuse it in second kernel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) pr_info("e820: reserve [mem %#010Lx-%#010Lx] for GART\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) aper_base, aper_base + aper_size - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) e820__range_add(aper_base, aper_size, E820_TYPE_RESERVED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) e820__update_table_print();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) if (valid_agp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) /* disable them all at first */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) for (i = 0; i < amd_nb_bus_dev_ranges[i].dev_limit; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) int bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) int dev_base, dev_limit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) bus = amd_nb_bus_dev_ranges[i].bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) dev_base = amd_nb_bus_dev_ranges[i].dev_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) dev_limit = amd_nb_bus_dev_ranges[i].dev_limit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) for (slot = dev_base; slot < dev_limit; slot++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) if (!early_is_amd_nb(read_pci_config(bus, slot, 3, 0x00)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) ctl = read_pci_config(bus, slot, 3, AMD64_GARTAPERTURECTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) ctl &= ~GARTEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) write_pci_config(bus, slot, 3, AMD64_GARTAPERTURECTL, ctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) static int __initdata printed_gart_size_msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) int __init gart_iommu_hole_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) u32 agp_aper_base = 0, agp_aper_order = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) u32 aper_size, aper_alloc = 0, aper_order = 0, last_aper_order = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) u64 aper_base, last_aper_base = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) int fix, slot, valid_agp = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) int i, node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) if (!amd_gart_present())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) if (gart_iommu_aperture_disabled || !fix_aperture ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) !early_pci_allowed())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) pr_info("Checking aperture...\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) if (!fallback_aper_force)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) agp_aper_base = search_agp_bridge(&agp_aper_order, &valid_agp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) fix = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) node = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) for (i = 0; i < amd_nb_bus_dev_ranges[i].dev_limit; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) int bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) int dev_base, dev_limit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) u32 ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) bus = amd_nb_bus_dev_ranges[i].bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) dev_base = amd_nb_bus_dev_ranges[i].dev_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) dev_limit = amd_nb_bus_dev_ranges[i].dev_limit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) for (slot = dev_base; slot < dev_limit; slot++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) if (!early_is_amd_nb(read_pci_config(bus, slot, 3, 0x00)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) iommu_detected = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) gart_iommu_aperture = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) x86_init.iommu.iommu_init = gart_iommu_init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) ctl = read_pci_config(bus, slot, 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) AMD64_GARTAPERTURECTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) * Before we do anything else disable the GART. It may
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) * still be enabled if we boot into a crash-kernel here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) * Reconfiguring the GART while it is enabled could have
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) * unknown side-effects.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) ctl &= ~GARTEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) write_pci_config(bus, slot, 3, AMD64_GARTAPERTURECTL, ctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) aper_order = (ctl >> 1) & 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) aper_size = (32 * 1024 * 1024) << aper_order;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) aper_base = read_pci_config(bus, slot, 3, AMD64_GARTAPERTUREBASE) & 0x7fff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) aper_base <<= 25;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) pr_info("Node %d: aperture [bus addr %#010Lx-%#010Lx] (%uMB)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) node, aper_base, aper_base + aper_size - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) aper_size >> 20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) node++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) if (!aperture_valid(aper_base, aper_size, 64<<20)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) if (valid_agp && agp_aper_base &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) agp_aper_base == aper_base &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) agp_aper_order == aper_order) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) /* the same between two setting from NB and agp */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) if (!no_iommu &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) max_pfn > MAX_DMA32_PFN &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) !printed_gart_size_msg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) pr_err("you are using iommu with agp, but GART size is less than 64MB\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) pr_err("please increase GART size in your BIOS setup\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) pr_err("if BIOS doesn't have that option, contact your HW vendor!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) printed_gart_size_msg = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) fix = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) if ((last_aper_order && aper_order != last_aper_order) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) (last_aper_base && aper_base != last_aper_base)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) fix = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) last_aper_order = aper_order;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) last_aper_base = aper_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) if (!fix && !fallback_aper_force) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) if (last_aper_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) * If this is the kdump kernel, the first kernel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) * may have allocated the range over its e820 RAM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) * and fixed up the northbridge
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) exclude_from_core(last_aper_base, last_aper_order);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) if (!fallback_aper_force) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) aper_alloc = agp_aper_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) aper_order = agp_aper_order;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) if (aper_alloc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) /* Got the aperture from the AGP bridge */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) } else if ((!no_iommu && max_pfn > MAX_DMA32_PFN) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) force_iommu ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) valid_agp ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) fallback_aper_force) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) pr_info("Your BIOS doesn't leave an aperture memory hole\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) pr_info("Please enable the IOMMU option in the BIOS setup\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) pr_info("This costs you %dMB of RAM\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) 32 << fallback_aper_order);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) aper_order = fallback_aper_order;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) aper_alloc = allocate_aperture();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) if (!aper_alloc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) * Could disable AGP and IOMMU here, but it's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) * probably not worth it. But the later users
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) * cannot deal with bad apertures and turning
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) * on the aperture over memory causes very
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) * strange problems, so it's better to panic
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) * early.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) panic("Not enough memory for aperture");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) * If this is the kdump kernel _and_ the first kernel did not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) * configure the aperture in the northbridge, this range may
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) * overlap with the first kernel's memory. We can't access the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) * range through vmcore even though it should be part of the dump.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) exclude_from_core(aper_alloc, aper_order);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) /* Fix up the north bridges */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) for (i = 0; i < amd_nb_bus_dev_ranges[i].dev_limit; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) int bus, dev_base, dev_limit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) * Don't enable translation yet but enable GART IO and CPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) * accesses and set DISTLBWALKPRB since GART table memory is UC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) u32 ctl = aper_order << 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) bus = amd_nb_bus_dev_ranges[i].bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) dev_base = amd_nb_bus_dev_ranges[i].dev_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) dev_limit = amd_nb_bus_dev_ranges[i].dev_limit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) for (slot = dev_base; slot < dev_limit; slot++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) if (!early_is_amd_nb(read_pci_config(bus, slot, 3, 0x00)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) write_pci_config(bus, slot, 3, AMD64_GARTAPERTURECTL, ctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) write_pci_config(bus, slot, 3, AMD64_GARTAPERTUREBASE, aper_alloc >> 25);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) set_up_gart_resume(aper_order, aper_alloc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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