Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * apb_timer.c: Driver for Langwell APB timers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * (C) Copyright 2009 Intel Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Author: Jacob Pan (jacob.jun.pan@intel.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * Note:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  * Langwell is the south complex of Intel Moorestown MID platform. There are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  * eight external timers in total that can be used by the operating system.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  * The timer information, such as frequency and addresses, is provided to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  * OS via SFI tables.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13)  * Timer interrupts are routed via FW/HW emulated IOAPIC independently via
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14)  * individual redirection table entries (RTE).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15)  * Unlike HPET, there is no master counter, therefore one of the timers are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16)  * used as clocksource. The overall allocation looks like:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17)  *  - timer 0 - NR_CPUs for per cpu timer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18)  *  - one timer for clocksource
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19)  *  - one timer for watchdog driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20)  * It is also worth notice that APB timer does not support true one-shot mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21)  * free-running mode will be used here to emulate one-shot mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22)  * APB timer can also be used as broadcast timer along with per cpu local APIC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23)  * timer, but by default APB timer has higher rating than local APIC timers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #include <linux/dw_apb_timer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #include <linux/pm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #include <linux/sfi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #include <linux/cpu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #include <asm/fixmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #include <asm/apb_timer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #include <asm/intel-mid.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #include <asm/time.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define APBT_CLOCKEVENT_RATING		110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define APBT_CLOCKSOURCE_RATING		250
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define APBT_CLOCKEVENT0_NUM   (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define APBT_CLOCKSOURCE_NUM   (2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) static phys_addr_t apbt_address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) static int apb_timer_block_enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) static void __iomem *apbt_virt_address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53)  * Common DW APB timer info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) static unsigned long apbt_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) struct apbt_dev {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	struct dw_apb_clock_event_device	*timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	unsigned int				num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	int					cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	unsigned int				irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	char					name[10];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) static struct dw_apb_clocksource *clocksource_apbt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) static inline void __iomem *adev_virt_addr(struct apbt_dev *adev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	return apbt_virt_address + adev->num * APBTMRS_REG_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) static DEFINE_PER_CPU(struct apbt_dev, cpu_apbt_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #ifdef CONFIG_SMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) static unsigned int apbt_num_timers_used;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) static inline void apbt_set_mapping(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	struct sfi_timer_table_entry *mtmr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	int phy_cs_timer_id = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	if (apbt_virt_address) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 		pr_debug("APBT base already mapped\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	mtmr = sfi_get_mtmr(APBT_CLOCKEVENT0_NUM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	if (mtmr == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 		printk(KERN_ERR "Failed to get MTMR %d from SFI\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 		       APBT_CLOCKEVENT0_NUM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	apbt_address = (phys_addr_t)mtmr->phys_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	if (!apbt_address) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 		printk(KERN_WARNING "No timer base from SFI, use default\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 		apbt_address = APBT_DEFAULT_BASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	apbt_virt_address = ioremap(apbt_address, APBT_MMAP_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	if (!apbt_virt_address) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 		pr_debug("Failed mapping APBT phy address at %lu\n",\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 			 (unsigned long)apbt_address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 		goto panic_noapbt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	apbt_freq = mtmr->freq_hz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	sfi_free_mtmr(mtmr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	/* Now figure out the physical timer id for clocksource device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	mtmr = sfi_get_mtmr(APBT_CLOCKSOURCE_NUM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	if (mtmr == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 		goto panic_noapbt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	/* Now figure out the physical timer id */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	pr_debug("Use timer %d for clocksource\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 		 (int)(mtmr->phys_addr & 0xff) / APBTMRS_REG_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	phy_cs_timer_id = (unsigned int)(mtmr->phys_addr & 0xff) /
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 		APBTMRS_REG_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	clocksource_apbt = dw_apb_clocksource_init(APBT_CLOCKSOURCE_RATING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 		"apbt0", apbt_virt_address + phy_cs_timer_id *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 		APBTMRS_REG_SIZE, apbt_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) panic_noapbt:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	panic("Failed to setup APB system timer\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) static inline void apbt_clear_mapping(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	iounmap(apbt_virt_address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	apbt_virt_address = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) static int __init apbt_clockevent_register(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	struct sfi_timer_table_entry *mtmr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	struct apbt_dev *adev = this_cpu_ptr(&cpu_apbt_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	mtmr = sfi_get_mtmr(APBT_CLOCKEVENT0_NUM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	if (mtmr == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 		printk(KERN_ERR "Failed to get MTMR %d from SFI\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 		       APBT_CLOCKEVENT0_NUM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	adev->num = smp_processor_id();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	adev->timer = dw_apb_clockevent_init(smp_processor_id(), "apbt0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 		intel_mid_timer_options == INTEL_MID_TIMER_LAPIC_APBT ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 		APBT_CLOCKEVENT_RATING - 100 : APBT_CLOCKEVENT_RATING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 		adev_virt_addr(adev), 0, apbt_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	/* Firmware does EOI handling for us. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	adev->timer->eoi = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	if (intel_mid_timer_options == INTEL_MID_TIMER_LAPIC_APBT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 		global_clock_event = &adev->timer->ced;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 		printk(KERN_DEBUG "%s clockevent registered as global\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 		       global_clock_event->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	dw_apb_clockevent_register(adev->timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	sfi_free_mtmr(mtmr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #ifdef CONFIG_SMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) static void apbt_setup_irq(struct apbt_dev *adev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	irq_modify_status(adev->irq, 0, IRQ_MOVE_PCNTXT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	irq_set_affinity(adev->irq, cpumask_of(adev->cpu));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) /* Should be called with per cpu */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) void apbt_setup_secondary_clock(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	struct apbt_dev *adev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	int cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	/* Don't register boot CPU clockevent */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	cpu = smp_processor_id();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	if (!cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	adev = this_cpu_ptr(&cpu_apbt_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	if (!adev->timer) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 		adev->timer = dw_apb_clockevent_init(cpu, adev->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 			APBT_CLOCKEVENT_RATING, adev_virt_addr(adev),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 			adev->irq, apbt_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 		adev->timer->eoi = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 		dw_apb_clockevent_resume(adev->timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	printk(KERN_INFO "Registering CPU %d clockevent device %s, cpu %08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	       cpu, adev->name, adev->cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	apbt_setup_irq(adev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	dw_apb_clockevent_register(adev->timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)  * this notify handler process CPU hotplug events. in case of S0i3, nonboot
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)  * cpus are disabled/enabled frequently, for performance reasons, we keep the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)  * per cpu timer irq registered so that we do need to do free_irq/request_irq.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)  * TODO: it might be more reliable to directly disable percpu clockevent device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)  * without the notifier chain. currently, cpu 0 may get interrupts from other
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)  * cpu timers during the offline process due to the ordering of notification.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)  * the extra interrupt is harmless.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) static int apbt_cpu_dead(unsigned int cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	struct apbt_dev *adev = &per_cpu(cpu_apbt_dev, cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	dw_apb_clockevent_pause(adev->timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	if (system_state == SYSTEM_RUNNING) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 		pr_debug("skipping APBT CPU %u offline\n", cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 		pr_debug("APBT clockevent for cpu %u offline\n", cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 		dw_apb_clockevent_stop(adev->timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) static __init int apbt_late_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	if (intel_mid_timer_options == INTEL_MID_TIMER_LAPIC_APBT ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 		!apb_timer_block_enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	return cpuhp_setup_state(CPUHP_X86_APB_DEAD, "x86/apb:dead", NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 				 apbt_cpu_dead);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) fs_initcall(apbt_late_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) void apbt_setup_secondary_clock(void) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #endif /* CONFIG_SMP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) static int apbt_clocksource_register(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	u64 start, now;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	u64 t1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	/* Start the counter, use timer 2 as source, timer 0/1 for event */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	dw_apb_clocksource_start(clocksource_apbt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	/* Verify whether apbt counter works */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	t1 = dw_apb_clocksource_read(clocksource_apbt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	start = rdtsc();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	 * We don't know the TSC frequency yet, but waiting for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	 * 200000 TSC cycles is safe:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	 * 4 GHz == 50us
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	 * 1 GHz == 200us
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 		rep_nop();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 		now = rdtsc();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	} while ((now - start) < 200000UL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	/* APBT is the only always on clocksource, it has to work! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	if (t1 == dw_apb_clocksource_read(clocksource_apbt))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 		panic("APBT counter not counting. APBT disabled\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	dw_apb_clocksource_register(clocksource_apbt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)  * Early setup the APBT timer, only use timer 0 for booting then switch to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)  * per CPU timer if possible.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)  * returns 1 if per cpu apbt is setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)  * returns 0 if no per cpu apbt is chosen
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)  * panic if set up failed, this is the only platform timer on Moorestown.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) void __init apbt_time_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #ifdef CONFIG_SMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	struct sfi_timer_table_entry *p_mtmr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	struct apbt_dev *adev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	if (apb_timer_block_enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	apbt_set_mapping();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	if (!apbt_virt_address)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 		goto out_noapbt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	 * Read the frequency and check for a sane value, for ESL model
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	 * we extend the possible clock range to allow time scaling.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	if (apbt_freq < APBT_MIN_FREQ || apbt_freq > APBT_MAX_FREQ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 		pr_debug("APBT has invalid freq 0x%lx\n", apbt_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 		goto out_noapbt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	if (apbt_clocksource_register()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 		pr_debug("APBT has failed to register clocksource\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 		goto out_noapbt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	if (!apbt_clockevent_register())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 		apb_timer_block_enabled = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 		pr_debug("APBT has failed to register clockevent\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 		goto out_noapbt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) #ifdef CONFIG_SMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	/* kernel cmdline disable apb timer, so we will use lapic timers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	if (intel_mid_timer_options == INTEL_MID_TIMER_LAPIC_APBT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 		printk(KERN_INFO "apbt: disabled per cpu timer\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	pr_debug("%s: %d CPUs online\n", __func__, num_online_cpus());
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	if (num_possible_cpus() <= sfi_mtimer_num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 		apbt_num_timers_used = num_possible_cpus();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 		apbt_num_timers_used = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 	pr_debug("%s: %d APB timers used\n", __func__, apbt_num_timers_used);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	/* here we set up per CPU timer data structure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	for (i = 0; i < apbt_num_timers_used; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 		adev = &per_cpu(cpu_apbt_dev, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 		adev->num = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 		adev->cpu = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 		p_mtmr = sfi_get_mtmr(i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 		if (p_mtmr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 			adev->irq = p_mtmr->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 		else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 			printk(KERN_ERR "Failed to get timer for cpu %d\n", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 		snprintf(adev->name, sizeof(adev->name) - 1, "apbt%d", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 	return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) out_noapbt:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 	apbt_clear_mapping();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 	apb_timer_block_enabled = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 	panic("failed to enable APB timer\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) }