^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * vmx.h: VMX Architecture related definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (c) 2004, Intel Corporation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * A few random additions are:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) 2006 Qumranet
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Avi Kivity <avi@qumranet.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Yaniv Kamay <yaniv@qumranet.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #ifndef VMX_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define VMX_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <uapi/asm/vmx.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <asm/vmxfeatures.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define VMCS_CONTROL_BIT(x) BIT(VMX_FEATURE_##x & 0x1f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * Definitions of Primary Processor-Based VM-Execution Controls.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define CPU_BASED_INTR_WINDOW_EXITING VMCS_CONTROL_BIT(INTR_WINDOW_EXITING)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define CPU_BASED_USE_TSC_OFFSETTING VMCS_CONTROL_BIT(USE_TSC_OFFSETTING)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define CPU_BASED_HLT_EXITING VMCS_CONTROL_BIT(HLT_EXITING)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define CPU_BASED_INVLPG_EXITING VMCS_CONTROL_BIT(INVLPG_EXITING)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define CPU_BASED_MWAIT_EXITING VMCS_CONTROL_BIT(MWAIT_EXITING)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define CPU_BASED_RDPMC_EXITING VMCS_CONTROL_BIT(RDPMC_EXITING)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define CPU_BASED_RDTSC_EXITING VMCS_CONTROL_BIT(RDTSC_EXITING)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define CPU_BASED_CR3_LOAD_EXITING VMCS_CONTROL_BIT(CR3_LOAD_EXITING)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define CPU_BASED_CR3_STORE_EXITING VMCS_CONTROL_BIT(CR3_STORE_EXITING)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define CPU_BASED_CR8_LOAD_EXITING VMCS_CONTROL_BIT(CR8_LOAD_EXITING)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define CPU_BASED_CR8_STORE_EXITING VMCS_CONTROL_BIT(CR8_STORE_EXITING)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define CPU_BASED_TPR_SHADOW VMCS_CONTROL_BIT(VIRTUAL_TPR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define CPU_BASED_NMI_WINDOW_EXITING VMCS_CONTROL_BIT(NMI_WINDOW_EXITING)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define CPU_BASED_MOV_DR_EXITING VMCS_CONTROL_BIT(MOV_DR_EXITING)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define CPU_BASED_UNCOND_IO_EXITING VMCS_CONTROL_BIT(UNCOND_IO_EXITING)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define CPU_BASED_USE_IO_BITMAPS VMCS_CONTROL_BIT(USE_IO_BITMAPS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define CPU_BASED_MONITOR_TRAP_FLAG VMCS_CONTROL_BIT(MONITOR_TRAP_FLAG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define CPU_BASED_USE_MSR_BITMAPS VMCS_CONTROL_BIT(USE_MSR_BITMAPS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define CPU_BASED_MONITOR_EXITING VMCS_CONTROL_BIT(MONITOR_EXITING)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define CPU_BASED_PAUSE_EXITING VMCS_CONTROL_BIT(PAUSE_EXITING)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define CPU_BASED_ACTIVATE_SECONDARY_CONTROLS VMCS_CONTROL_BIT(SEC_CONTROLS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR 0x0401e172
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * Definitions of Secondary Processor-Based VM-Execution Controls.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES VMCS_CONTROL_BIT(VIRT_APIC_ACCESSES)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define SECONDARY_EXEC_ENABLE_EPT VMCS_CONTROL_BIT(EPT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define SECONDARY_EXEC_DESC VMCS_CONTROL_BIT(DESC_EXITING)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define SECONDARY_EXEC_ENABLE_RDTSCP VMCS_CONTROL_BIT(RDTSCP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE VMCS_CONTROL_BIT(VIRTUAL_X2APIC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define SECONDARY_EXEC_ENABLE_VPID VMCS_CONTROL_BIT(VPID)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define SECONDARY_EXEC_WBINVD_EXITING VMCS_CONTROL_BIT(WBINVD_EXITING)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define SECONDARY_EXEC_UNRESTRICTED_GUEST VMCS_CONTROL_BIT(UNRESTRICTED_GUEST)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define SECONDARY_EXEC_APIC_REGISTER_VIRT VMCS_CONTROL_BIT(APIC_REGISTER_VIRT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY VMCS_CONTROL_BIT(VIRT_INTR_DELIVERY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define SECONDARY_EXEC_PAUSE_LOOP_EXITING VMCS_CONTROL_BIT(PAUSE_LOOP_EXITING)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define SECONDARY_EXEC_RDRAND_EXITING VMCS_CONTROL_BIT(RDRAND_EXITING)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define SECONDARY_EXEC_ENABLE_INVPCID VMCS_CONTROL_BIT(INVPCID)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define SECONDARY_EXEC_ENABLE_VMFUNC VMCS_CONTROL_BIT(VMFUNC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define SECONDARY_EXEC_SHADOW_VMCS VMCS_CONTROL_BIT(SHADOW_VMCS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define SECONDARY_EXEC_ENCLS_EXITING VMCS_CONTROL_BIT(ENCLS_EXITING)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define SECONDARY_EXEC_RDSEED_EXITING VMCS_CONTROL_BIT(RDSEED_EXITING)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define SECONDARY_EXEC_ENABLE_PML VMCS_CONTROL_BIT(PAGE_MOD_LOGGING)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define SECONDARY_EXEC_PT_CONCEAL_VMX VMCS_CONTROL_BIT(PT_CONCEAL_VMX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define SECONDARY_EXEC_XSAVES VMCS_CONTROL_BIT(XSAVES)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define SECONDARY_EXEC_MODE_BASED_EPT_EXEC VMCS_CONTROL_BIT(MODE_BASED_EPT_EXEC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define SECONDARY_EXEC_PT_USE_GPA VMCS_CONTROL_BIT(PT_USE_GPA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define SECONDARY_EXEC_TSC_SCALING VMCS_CONTROL_BIT(TSC_SCALING)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE VMCS_CONTROL_BIT(USR_WAIT_PAUSE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define PIN_BASED_EXT_INTR_MASK VMCS_CONTROL_BIT(INTR_EXITING)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define PIN_BASED_NMI_EXITING VMCS_CONTROL_BIT(NMI_EXITING)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define PIN_BASED_VIRTUAL_NMIS VMCS_CONTROL_BIT(VIRTUAL_NMIS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define PIN_BASED_VMX_PREEMPTION_TIMER VMCS_CONTROL_BIT(PREEMPTION_TIMER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define PIN_BASED_POSTED_INTR VMCS_CONTROL_BIT(POSTED_INTR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR 0x00000016
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define VM_EXIT_SAVE_DEBUG_CONTROLS 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define VM_EXIT_HOST_ADDR_SPACE_SIZE 0x00000200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL 0x00001000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define VM_EXIT_ACK_INTR_ON_EXIT 0x00008000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define VM_EXIT_SAVE_IA32_PAT 0x00040000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define VM_EXIT_LOAD_IA32_PAT 0x00080000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define VM_EXIT_SAVE_IA32_EFER 0x00100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define VM_EXIT_LOAD_IA32_EFER 0x00200000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define VM_EXIT_SAVE_VMX_PREEMPTION_TIMER 0x00400000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define VM_EXIT_CLEAR_BNDCFGS 0x00800000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define VM_EXIT_PT_CONCEAL_PIP 0x01000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define VM_EXIT_CLEAR_IA32_RTIT_CTL 0x02000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR 0x00036dff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define VM_ENTRY_LOAD_DEBUG_CONTROLS 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define VM_ENTRY_IA32E_MODE 0x00000200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define VM_ENTRY_SMM 0x00000400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define VM_ENTRY_DEACT_DUAL_MONITOR 0x00000800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL 0x00002000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define VM_ENTRY_LOAD_IA32_PAT 0x00004000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define VM_ENTRY_LOAD_IA32_EFER 0x00008000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define VM_ENTRY_LOAD_BNDCFGS 0x00010000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define VM_ENTRY_PT_CONCEAL_PIP 0x00020000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define VM_ENTRY_LOAD_IA32_RTIT_CTL 0x00040000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR 0x000011ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define VMX_MISC_PREEMPTION_TIMER_RATE_MASK 0x0000001f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define VMX_MISC_SAVE_EFER_LMA 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define VMX_MISC_ACTIVITY_HLT 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define VMX_MISC_ZERO_LEN_INS 0x40000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define VMX_MISC_MSR_LIST_MULTIPLIER 512
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) /* VMFUNC functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define VMFUNC_CONTROL_BIT(x) BIT((VMX_FEATURE_##x & 0x1f) - 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define VMX_VMFUNC_EPTP_SWITCHING VMFUNC_CONTROL_BIT(EPTP_SWITCHING)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define VMFUNC_EPTP_ENTRIES 512
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) static inline u32 vmx_basic_vmcs_revision_id(u64 vmx_basic)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) return vmx_basic & GENMASK_ULL(30, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) static inline u32 vmx_basic_vmcs_size(u64 vmx_basic)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) return (vmx_basic & GENMASK_ULL(44, 32)) >> 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) static inline int vmx_misc_preemption_timer_rate(u64 vmx_misc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) return vmx_misc & VMX_MISC_PREEMPTION_TIMER_RATE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) static inline int vmx_misc_cr3_count(u64 vmx_misc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) return (vmx_misc & GENMASK_ULL(24, 16)) >> 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) static inline int vmx_misc_max_msr(u64 vmx_misc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) return (vmx_misc & GENMASK_ULL(27, 25)) >> 25;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) static inline int vmx_misc_mseg_revid(u64 vmx_misc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) return (vmx_misc & GENMASK_ULL(63, 32)) >> 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) /* VMCS Encodings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) enum vmcs_field {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) VIRTUAL_PROCESSOR_ID = 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) POSTED_INTR_NV = 0x00000002,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) GUEST_ES_SELECTOR = 0x00000800,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) GUEST_CS_SELECTOR = 0x00000802,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) GUEST_SS_SELECTOR = 0x00000804,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) GUEST_DS_SELECTOR = 0x00000806,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) GUEST_FS_SELECTOR = 0x00000808,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) GUEST_GS_SELECTOR = 0x0000080a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) GUEST_LDTR_SELECTOR = 0x0000080c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) GUEST_TR_SELECTOR = 0x0000080e,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) GUEST_INTR_STATUS = 0x00000810,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) GUEST_PML_INDEX = 0x00000812,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) HOST_ES_SELECTOR = 0x00000c00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) HOST_CS_SELECTOR = 0x00000c02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) HOST_SS_SELECTOR = 0x00000c04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) HOST_DS_SELECTOR = 0x00000c06,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) HOST_FS_SELECTOR = 0x00000c08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) HOST_GS_SELECTOR = 0x00000c0a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) HOST_TR_SELECTOR = 0x00000c0c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) IO_BITMAP_A = 0x00002000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) IO_BITMAP_A_HIGH = 0x00002001,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) IO_BITMAP_B = 0x00002002,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) IO_BITMAP_B_HIGH = 0x00002003,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) MSR_BITMAP = 0x00002004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) MSR_BITMAP_HIGH = 0x00002005,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) VM_EXIT_MSR_STORE_ADDR = 0x00002006,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) VM_EXIT_MSR_STORE_ADDR_HIGH = 0x00002007,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) VM_EXIT_MSR_LOAD_ADDR = 0x00002008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) VM_EXIT_MSR_LOAD_ADDR_HIGH = 0x00002009,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) VM_ENTRY_MSR_LOAD_ADDR = 0x0000200a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) VM_ENTRY_MSR_LOAD_ADDR_HIGH = 0x0000200b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) PML_ADDRESS = 0x0000200e,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) PML_ADDRESS_HIGH = 0x0000200f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) TSC_OFFSET = 0x00002010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) TSC_OFFSET_HIGH = 0x00002011,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) VIRTUAL_APIC_PAGE_ADDR = 0x00002012,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) VIRTUAL_APIC_PAGE_ADDR_HIGH = 0x00002013,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) APIC_ACCESS_ADDR = 0x00002014,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) APIC_ACCESS_ADDR_HIGH = 0x00002015,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) POSTED_INTR_DESC_ADDR = 0x00002016,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) POSTED_INTR_DESC_ADDR_HIGH = 0x00002017,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) VM_FUNCTION_CONTROL = 0x00002018,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) VM_FUNCTION_CONTROL_HIGH = 0x00002019,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) EPT_POINTER = 0x0000201a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) EPT_POINTER_HIGH = 0x0000201b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) EOI_EXIT_BITMAP0 = 0x0000201c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) EOI_EXIT_BITMAP0_HIGH = 0x0000201d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) EOI_EXIT_BITMAP1 = 0x0000201e,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) EOI_EXIT_BITMAP1_HIGH = 0x0000201f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) EOI_EXIT_BITMAP2 = 0x00002020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) EOI_EXIT_BITMAP2_HIGH = 0x00002021,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) EOI_EXIT_BITMAP3 = 0x00002022,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) EOI_EXIT_BITMAP3_HIGH = 0x00002023,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) EPTP_LIST_ADDRESS = 0x00002024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) EPTP_LIST_ADDRESS_HIGH = 0x00002025,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) VMREAD_BITMAP = 0x00002026,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) VMREAD_BITMAP_HIGH = 0x00002027,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) VMWRITE_BITMAP = 0x00002028,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) VMWRITE_BITMAP_HIGH = 0x00002029,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) XSS_EXIT_BITMAP = 0x0000202C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) XSS_EXIT_BITMAP_HIGH = 0x0000202D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) ENCLS_EXITING_BITMAP = 0x0000202E,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) ENCLS_EXITING_BITMAP_HIGH = 0x0000202F,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) TSC_MULTIPLIER = 0x00002032,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) TSC_MULTIPLIER_HIGH = 0x00002033,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) GUEST_PHYSICAL_ADDRESS = 0x00002400,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) GUEST_PHYSICAL_ADDRESS_HIGH = 0x00002401,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) VMCS_LINK_POINTER = 0x00002800,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) VMCS_LINK_POINTER_HIGH = 0x00002801,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) GUEST_IA32_DEBUGCTL = 0x00002802,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) GUEST_IA32_DEBUGCTL_HIGH = 0x00002803,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) GUEST_IA32_PAT = 0x00002804,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) GUEST_IA32_PAT_HIGH = 0x00002805,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) GUEST_IA32_EFER = 0x00002806,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) GUEST_IA32_EFER_HIGH = 0x00002807,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) GUEST_IA32_PERF_GLOBAL_CTRL = 0x00002808,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) GUEST_IA32_PERF_GLOBAL_CTRL_HIGH= 0x00002809,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) GUEST_PDPTR0 = 0x0000280a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) GUEST_PDPTR0_HIGH = 0x0000280b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) GUEST_PDPTR1 = 0x0000280c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) GUEST_PDPTR1_HIGH = 0x0000280d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) GUEST_PDPTR2 = 0x0000280e,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) GUEST_PDPTR2_HIGH = 0x0000280f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) GUEST_PDPTR3 = 0x00002810,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) GUEST_PDPTR3_HIGH = 0x00002811,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) GUEST_BNDCFGS = 0x00002812,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) GUEST_BNDCFGS_HIGH = 0x00002813,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) GUEST_IA32_RTIT_CTL = 0x00002814,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) GUEST_IA32_RTIT_CTL_HIGH = 0x00002815,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) HOST_IA32_PAT = 0x00002c00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) HOST_IA32_PAT_HIGH = 0x00002c01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) HOST_IA32_EFER = 0x00002c02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) HOST_IA32_EFER_HIGH = 0x00002c03,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) HOST_IA32_PERF_GLOBAL_CTRL = 0x00002c04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) HOST_IA32_PERF_GLOBAL_CTRL_HIGH = 0x00002c05,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) PIN_BASED_VM_EXEC_CONTROL = 0x00004000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) CPU_BASED_VM_EXEC_CONTROL = 0x00004002,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) EXCEPTION_BITMAP = 0x00004004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) PAGE_FAULT_ERROR_CODE_MASK = 0x00004006,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) PAGE_FAULT_ERROR_CODE_MATCH = 0x00004008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) CR3_TARGET_COUNT = 0x0000400a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) VM_EXIT_CONTROLS = 0x0000400c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) VM_EXIT_MSR_STORE_COUNT = 0x0000400e,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) VM_EXIT_MSR_LOAD_COUNT = 0x00004010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) VM_ENTRY_CONTROLS = 0x00004012,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) VM_ENTRY_MSR_LOAD_COUNT = 0x00004014,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) VM_ENTRY_INTR_INFO_FIELD = 0x00004016,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) VM_ENTRY_EXCEPTION_ERROR_CODE = 0x00004018,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) VM_ENTRY_INSTRUCTION_LEN = 0x0000401a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) TPR_THRESHOLD = 0x0000401c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) SECONDARY_VM_EXEC_CONTROL = 0x0000401e,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) PLE_GAP = 0x00004020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) PLE_WINDOW = 0x00004022,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) VM_INSTRUCTION_ERROR = 0x00004400,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) VM_EXIT_REASON = 0x00004402,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) VM_EXIT_INTR_INFO = 0x00004404,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) VM_EXIT_INTR_ERROR_CODE = 0x00004406,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) IDT_VECTORING_INFO_FIELD = 0x00004408,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) IDT_VECTORING_ERROR_CODE = 0x0000440a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) VM_EXIT_INSTRUCTION_LEN = 0x0000440c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) VMX_INSTRUCTION_INFO = 0x0000440e,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) GUEST_ES_LIMIT = 0x00004800,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) GUEST_CS_LIMIT = 0x00004802,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) GUEST_SS_LIMIT = 0x00004804,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) GUEST_DS_LIMIT = 0x00004806,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) GUEST_FS_LIMIT = 0x00004808,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) GUEST_GS_LIMIT = 0x0000480a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) GUEST_LDTR_LIMIT = 0x0000480c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) GUEST_TR_LIMIT = 0x0000480e,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) GUEST_GDTR_LIMIT = 0x00004810,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) GUEST_IDTR_LIMIT = 0x00004812,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) GUEST_ES_AR_BYTES = 0x00004814,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) GUEST_CS_AR_BYTES = 0x00004816,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) GUEST_SS_AR_BYTES = 0x00004818,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) GUEST_DS_AR_BYTES = 0x0000481a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) GUEST_FS_AR_BYTES = 0x0000481c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) GUEST_GS_AR_BYTES = 0x0000481e,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) GUEST_LDTR_AR_BYTES = 0x00004820,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) GUEST_TR_AR_BYTES = 0x00004822,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) GUEST_INTERRUPTIBILITY_INFO = 0x00004824,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) GUEST_ACTIVITY_STATE = 0X00004826,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) GUEST_SYSENTER_CS = 0x0000482A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) VMX_PREEMPTION_TIMER_VALUE = 0x0000482E,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) HOST_IA32_SYSENTER_CS = 0x00004c00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) CR0_GUEST_HOST_MASK = 0x00006000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) CR4_GUEST_HOST_MASK = 0x00006002,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) CR0_READ_SHADOW = 0x00006004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) CR4_READ_SHADOW = 0x00006006,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) CR3_TARGET_VALUE0 = 0x00006008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) CR3_TARGET_VALUE1 = 0x0000600a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) CR3_TARGET_VALUE2 = 0x0000600c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) CR3_TARGET_VALUE3 = 0x0000600e,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) EXIT_QUALIFICATION = 0x00006400,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) GUEST_LINEAR_ADDRESS = 0x0000640a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) GUEST_CR0 = 0x00006800,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) GUEST_CR3 = 0x00006802,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) GUEST_CR4 = 0x00006804,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) GUEST_ES_BASE = 0x00006806,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) GUEST_CS_BASE = 0x00006808,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) GUEST_SS_BASE = 0x0000680a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) GUEST_DS_BASE = 0x0000680c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) GUEST_FS_BASE = 0x0000680e,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) GUEST_GS_BASE = 0x00006810,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) GUEST_LDTR_BASE = 0x00006812,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) GUEST_TR_BASE = 0x00006814,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) GUEST_GDTR_BASE = 0x00006816,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) GUEST_IDTR_BASE = 0x00006818,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) GUEST_DR7 = 0x0000681a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) GUEST_RSP = 0x0000681c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) GUEST_RIP = 0x0000681e,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) GUEST_RFLAGS = 0x00006820,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) GUEST_PENDING_DBG_EXCEPTIONS = 0x00006822,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) GUEST_SYSENTER_ESP = 0x00006824,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) GUEST_SYSENTER_EIP = 0x00006826,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) HOST_CR0 = 0x00006c00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) HOST_CR3 = 0x00006c02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) HOST_CR4 = 0x00006c04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) HOST_FS_BASE = 0x00006c06,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) HOST_GS_BASE = 0x00006c08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) HOST_TR_BASE = 0x00006c0a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) HOST_GDTR_BASE = 0x00006c0c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) HOST_IDTR_BASE = 0x00006c0e,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) HOST_IA32_SYSENTER_ESP = 0x00006c10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) HOST_IA32_SYSENTER_EIP = 0x00006c12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) HOST_RSP = 0x00006c14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) HOST_RIP = 0x00006c16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) * Interruption-information format
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) #define INTR_INFO_VECTOR_MASK 0xff /* 7:0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) #define INTR_INFO_INTR_TYPE_MASK 0x700 /* 10:8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) #define INTR_INFO_DELIVER_CODE_MASK 0x800 /* 11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) #define INTR_INFO_UNBLOCK_NMI 0x1000 /* 12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) #define INTR_INFO_VALID_MASK 0x80000000 /* 31 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) #define INTR_INFO_RESVD_BITS_MASK 0x7ffff000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) #define VECTORING_INFO_VECTOR_MASK INTR_INFO_VECTOR_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) #define VECTORING_INFO_TYPE_MASK INTR_INFO_INTR_TYPE_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) #define VECTORING_INFO_DELIVER_CODE_MASK INTR_INFO_DELIVER_CODE_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) #define VECTORING_INFO_VALID_MASK INTR_INFO_VALID_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) #define INTR_TYPE_EXT_INTR (0 << 8) /* external interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) #define INTR_TYPE_RESERVED (1 << 8) /* reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) #define INTR_TYPE_NMI_INTR (2 << 8) /* NMI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) #define INTR_TYPE_HARD_EXCEPTION (3 << 8) /* processor exception */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) #define INTR_TYPE_SOFT_INTR (4 << 8) /* software interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) #define INTR_TYPE_PRIV_SW_EXCEPTION (5 << 8) /* ICE breakpoint - undocumented */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) #define INTR_TYPE_SOFT_EXCEPTION (6 << 8) /* software exception */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) #define INTR_TYPE_OTHER_EVENT (7 << 8) /* other event */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) /* GUEST_INTERRUPTIBILITY_INFO flags. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) #define GUEST_INTR_STATE_STI 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) #define GUEST_INTR_STATE_MOV_SS 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) #define GUEST_INTR_STATE_SMI 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) #define GUEST_INTR_STATE_NMI 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) /* GUEST_ACTIVITY_STATE flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) #define GUEST_ACTIVITY_ACTIVE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) #define GUEST_ACTIVITY_HLT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) #define GUEST_ACTIVITY_SHUTDOWN 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) #define GUEST_ACTIVITY_WAIT_SIPI 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) * Exit Qualifications for MOV for Control Register Access
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) #define CONTROL_REG_ACCESS_NUM 0x7 /* 2:0, number of control reg.*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) #define CONTROL_REG_ACCESS_TYPE 0x30 /* 5:4, access type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) #define CONTROL_REG_ACCESS_REG 0xf00 /* 10:8, general purpose reg. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) #define LMSW_SOURCE_DATA_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) #define LMSW_SOURCE_DATA (0xFFFF << LMSW_SOURCE_DATA_SHIFT) /* 16:31 lmsw source */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) #define REG_EAX (0 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) #define REG_ECX (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) #define REG_EDX (2 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) #define REG_EBX (3 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) #define REG_ESP (4 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) #define REG_EBP (5 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) #define REG_ESI (6 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) #define REG_EDI (7 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) #define REG_R8 (8 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) #define REG_R9 (9 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) #define REG_R10 (10 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) #define REG_R11 (11 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) #define REG_R12 (12 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) #define REG_R13 (13 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) #define REG_R14 (14 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) #define REG_R15 (15 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) * Exit Qualifications for MOV for Debug Register Access
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) #define DEBUG_REG_ACCESS_NUM 0x7 /* 2:0, number of debug reg. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) #define DEBUG_REG_ACCESS_TYPE 0x10 /* 4, direction of access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) #define TYPE_MOV_TO_DR (0 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) #define TYPE_MOV_FROM_DR (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) #define DEBUG_REG_ACCESS_REG(eq) (((eq) >> 8) & 0xf) /* 11:8, general purpose reg. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) * Exit Qualifications for APIC-Access
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) #define APIC_ACCESS_OFFSET 0xfff /* 11:0, offset within the APIC page */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) #define APIC_ACCESS_TYPE 0xf000 /* 15:12, access type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) #define TYPE_LINEAR_APIC_INST_READ (0 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) #define TYPE_LINEAR_APIC_INST_WRITE (1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) #define TYPE_LINEAR_APIC_INST_FETCH (2 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) #define TYPE_LINEAR_APIC_EVENT (3 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) #define TYPE_PHYSICAL_APIC_EVENT (10 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) #define TYPE_PHYSICAL_APIC_INST (15 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) /* segment AR in VMCS -- these are different from what LAR reports */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) #define VMX_SEGMENT_AR_L_MASK (1 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) #define VMX_AR_TYPE_ACCESSES_MASK 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) #define VMX_AR_TYPE_READABLE_MASK (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) #define VMX_AR_TYPE_WRITEABLE_MASK (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) #define VMX_AR_TYPE_CODE_MASK (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) #define VMX_AR_TYPE_MASK 0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) #define VMX_AR_TYPE_BUSY_64_TSS 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) #define VMX_AR_TYPE_BUSY_32_TSS 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) #define VMX_AR_TYPE_BUSY_16_TSS 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) #define VMX_AR_TYPE_LDT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) #define VMX_AR_UNUSABLE_MASK (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) #define VMX_AR_S_MASK (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) #define VMX_AR_P_MASK (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) #define VMX_AR_L_MASK (1 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) #define VMX_AR_DB_MASK (1 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) #define VMX_AR_G_MASK (1 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) #define VMX_AR_DPL_SHIFT 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) #define VMX_AR_DPL(ar) (((ar) >> VMX_AR_DPL_SHIFT) & 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) #define VMX_AR_RESERVD_MASK 0xfffe0f00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) #define TSS_PRIVATE_MEMSLOT (KVM_USER_MEM_SLOTS + 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) #define APIC_ACCESS_PAGE_PRIVATE_MEMSLOT (KVM_USER_MEM_SLOTS + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) #define IDENTITY_PAGETABLE_PRIVATE_MEMSLOT (KVM_USER_MEM_SLOTS + 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) #define VMX_NR_VPIDS (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) #define VMX_VPID_EXTENT_INDIVIDUAL_ADDR 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) #define VMX_VPID_EXTENT_SINGLE_CONTEXT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) #define VMX_VPID_EXTENT_ALL_CONTEXT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) #define VMX_VPID_EXTENT_SINGLE_NON_GLOBAL 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) #define VMX_EPT_EXTENT_CONTEXT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) #define VMX_EPT_EXTENT_GLOBAL 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) #define VMX_EPT_EXTENT_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) #define VMX_EPT_EXECUTE_ONLY_BIT (1ull)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) #define VMX_EPT_PAGE_WALK_4_BIT (1ull << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) #define VMX_EPT_PAGE_WALK_5_BIT (1ull << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) #define VMX_EPTP_UC_BIT (1ull << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) #define VMX_EPTP_WB_BIT (1ull << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) #define VMX_EPT_2MB_PAGE_BIT (1ull << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) #define VMX_EPT_1GB_PAGE_BIT (1ull << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) #define VMX_EPT_INVEPT_BIT (1ull << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) #define VMX_EPT_AD_BIT (1ull << 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) #define VMX_EPT_EXTENT_CONTEXT_BIT (1ull << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) #define VMX_EPT_EXTENT_GLOBAL_BIT (1ull << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) #define VMX_VPID_INVVPID_BIT (1ull << 0) /* (32 - 32) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) #define VMX_VPID_EXTENT_INDIVIDUAL_ADDR_BIT (1ull << 8) /* (40 - 32) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) #define VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT (1ull << 9) /* (41 - 32) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) #define VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT (1ull << 10) /* (42 - 32) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) #define VMX_VPID_EXTENT_SINGLE_NON_GLOBAL_BIT (1ull << 11) /* (43 - 32) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) #define VMX_EPT_MT_EPTE_SHIFT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) #define VMX_EPTP_PWL_MASK 0x38ull
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) #define VMX_EPTP_PWL_4 0x18ull
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) #define VMX_EPTP_PWL_5 0x20ull
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) #define VMX_EPTP_AD_ENABLE_BIT (1ull << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) #define VMX_EPTP_MT_MASK 0x7ull
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) #define VMX_EPTP_MT_WB 0x6ull
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) #define VMX_EPTP_MT_UC 0x0ull
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) #define VMX_EPT_READABLE_MASK 0x1ull
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) #define VMX_EPT_WRITABLE_MASK 0x2ull
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) #define VMX_EPT_EXECUTABLE_MASK 0x4ull
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) #define VMX_EPT_IPAT_BIT (1ull << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) #define VMX_EPT_ACCESS_BIT (1ull << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) #define VMX_EPT_DIRTY_BIT (1ull << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) #define VMX_EPT_RWX_MASK (VMX_EPT_READABLE_MASK | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) VMX_EPT_WRITABLE_MASK | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) VMX_EPT_EXECUTABLE_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) #define VMX_EPT_MT_MASK (7ull << VMX_EPT_MT_EPTE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) static inline u8 vmx_eptp_page_walk_level(u64 eptp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) u64 encoded_level = eptp & VMX_EPTP_PWL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) if (encoded_level == VMX_EPTP_PWL_5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) return 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) /* @eptp must be pre-validated by the caller. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) WARN_ON_ONCE(encoded_level != VMX_EPTP_PWL_4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) return 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) /* The mask to use to trigger an EPT Misconfiguration in order to track MMIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) #define VMX_EPT_MISCONFIG_WX_VALUE (VMX_EPT_WRITABLE_MASK | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) VMX_EPT_EXECUTABLE_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) #define VMX_EPT_IDENTITY_PAGETABLE_ADDR 0xfffbc000ul
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) struct vmx_msr_entry {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) u32 index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) u32 reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) u64 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) } __aligned(16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) * Exit Qualifications for entry failure during or after loading guest state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) enum vm_entry_failure_code {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) ENTRY_FAIL_DEFAULT = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) ENTRY_FAIL_PDPTE = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) ENTRY_FAIL_NMI = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) ENTRY_FAIL_VMCS_LINK_PTR = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) * Exit Qualifications for EPT Violations
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) #define EPT_VIOLATION_ACC_READ_BIT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) #define EPT_VIOLATION_ACC_WRITE_BIT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) #define EPT_VIOLATION_ACC_INSTR_BIT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) #define EPT_VIOLATION_READABLE_BIT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) #define EPT_VIOLATION_WRITABLE_BIT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) #define EPT_VIOLATION_EXECUTABLE_BIT 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) #define EPT_VIOLATION_GVA_TRANSLATED_BIT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) #define EPT_VIOLATION_ACC_READ (1 << EPT_VIOLATION_ACC_READ_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) #define EPT_VIOLATION_ACC_WRITE (1 << EPT_VIOLATION_ACC_WRITE_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) #define EPT_VIOLATION_ACC_INSTR (1 << EPT_VIOLATION_ACC_INSTR_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) #define EPT_VIOLATION_READABLE (1 << EPT_VIOLATION_READABLE_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) #define EPT_VIOLATION_WRITABLE (1 << EPT_VIOLATION_WRITABLE_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) #define EPT_VIOLATION_EXECUTABLE (1 << EPT_VIOLATION_EXECUTABLE_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) #define EPT_VIOLATION_GVA_TRANSLATED (1 << EPT_VIOLATION_GVA_TRANSLATED_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) * VM-instruction error numbers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) enum vm_instruction_error_number {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) VMXERR_VMCALL_IN_VMX_ROOT_OPERATION = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) VMXERR_VMCLEAR_INVALID_ADDRESS = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) VMXERR_VMCLEAR_VMXON_POINTER = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) VMXERR_VMLAUNCH_NONCLEAR_VMCS = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) VMXERR_VMRESUME_NONLAUNCHED_VMCS = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) VMXERR_VMRESUME_AFTER_VMXOFF = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) VMXERR_ENTRY_INVALID_CONTROL_FIELD = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) VMXERR_ENTRY_INVALID_HOST_STATE_FIELD = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) VMXERR_VMPTRLD_INVALID_ADDRESS = 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) VMXERR_VMPTRLD_VMXON_POINTER = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID = 11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) VMXERR_UNSUPPORTED_VMCS_COMPONENT = 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT = 13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) VMXERR_VMXON_IN_VMX_ROOT_OPERATION = 15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) VMXERR_ENTRY_INVALID_EXECUTIVE_VMCS_POINTER = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) VMXERR_ENTRY_NONLAUNCHED_EXECUTIVE_VMCS = 17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) VMXERR_ENTRY_EXECUTIVE_VMCS_POINTER_NOT_VMXON_POINTER = 18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) VMXERR_VMCALL_NONCLEAR_VMCS = 19,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) VMXERR_VMCALL_INVALID_VM_EXIT_CONTROL_FIELDS = 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) VMXERR_VMCALL_INCORRECT_MSEG_REVISION_ID = 22,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) VMXERR_VMXOFF_UNDER_DUAL_MONITOR_TREATMENT_OF_SMIS_AND_SMM = 23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) VMXERR_VMCALL_INVALID_SMM_MONITOR_FEATURES = 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) VMXERR_ENTRY_INVALID_VM_EXECUTION_CONTROL_FIELDS_IN_EXECUTIVE_VMCS = 25,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) VMXERR_ENTRY_EVENTS_BLOCKED_BY_MOV_SS = 26,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID = 28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) * VM-instruction errors that can be encountered on VM-Enter, used to trace
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) * nested VM-Enter failures reported by hardware. Errors unique to VM-Enter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) * from a SMI Transfer Monitor are not included as things have gone seriously
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) * sideways if we get one of those...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) #define VMX_VMENTER_INSTRUCTION_ERRORS \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) { VMXERR_VMLAUNCH_NONCLEAR_VMCS, "VMLAUNCH_NONCLEAR_VMCS" }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) { VMXERR_VMRESUME_NONLAUNCHED_VMCS, "VMRESUME_NONLAUNCHED_VMCS" }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) { VMXERR_VMRESUME_AFTER_VMXOFF, "VMRESUME_AFTER_VMXOFF" }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) { VMXERR_ENTRY_INVALID_CONTROL_FIELD, "VMENTRY_INVALID_CONTROL_FIELD" }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) { VMXERR_ENTRY_INVALID_HOST_STATE_FIELD, "VMENTRY_INVALID_HOST_STATE_FIELD" }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) { VMXERR_ENTRY_EVENTS_BLOCKED_BY_MOV_SS, "VMENTRY_EVENTS_BLOCKED_BY_MOV_SS" }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) enum vmx_l1d_flush_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) VMENTER_L1D_FLUSH_AUTO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) VMENTER_L1D_FLUSH_NEVER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) VMENTER_L1D_FLUSH_COND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) VMENTER_L1D_FLUSH_ALWAYS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) VMENTER_L1D_FLUSH_EPT_DISABLED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) VMENTER_L1D_FLUSH_NOT_REQUIRED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) extern enum vmx_l1d_flush_state l1tf_vmx_mitigation;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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