^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) #ifndef __SVM_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) #define __SVM_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #include <uapi/asm/svm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <uapi/asm/kvm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * 32-bit intercept words in the VMCB Control Area, starting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * at Byte offset 000h.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) enum intercept_words {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) INTERCEPT_CR = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) INTERCEPT_DR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) INTERCEPT_EXCEPTION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) INTERCEPT_WORD3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) INTERCEPT_WORD4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) INTERCEPT_WORD5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) MAX_INTERCEPT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) /* Byte offset 000h (word 0) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) INTERCEPT_CR0_READ = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) INTERCEPT_CR3_READ = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) INTERCEPT_CR4_READ = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) INTERCEPT_CR8_READ = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) INTERCEPT_CR0_WRITE = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) INTERCEPT_CR3_WRITE = 16 + 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) INTERCEPT_CR4_WRITE = 16 + 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) INTERCEPT_CR8_WRITE = 16 + 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) /* Byte offset 004h (word 1) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) INTERCEPT_DR0_READ = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) INTERCEPT_DR1_READ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) INTERCEPT_DR2_READ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) INTERCEPT_DR3_READ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) INTERCEPT_DR4_READ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) INTERCEPT_DR5_READ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) INTERCEPT_DR6_READ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) INTERCEPT_DR7_READ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) INTERCEPT_DR0_WRITE = 48,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) INTERCEPT_DR1_WRITE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) INTERCEPT_DR2_WRITE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) INTERCEPT_DR3_WRITE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) INTERCEPT_DR4_WRITE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) INTERCEPT_DR5_WRITE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) INTERCEPT_DR6_WRITE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) INTERCEPT_DR7_WRITE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /* Byte offset 008h (word 2) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) INTERCEPT_EXCEPTION_OFFSET = 64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) /* Byte offset 00Ch (word 3) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) INTERCEPT_INTR = 96,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) INTERCEPT_NMI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) INTERCEPT_SMI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) INTERCEPT_INIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) INTERCEPT_VINTR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) INTERCEPT_SELECTIVE_CR0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) INTERCEPT_STORE_IDTR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) INTERCEPT_STORE_GDTR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) INTERCEPT_STORE_LDTR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) INTERCEPT_STORE_TR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) INTERCEPT_LOAD_IDTR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) INTERCEPT_LOAD_GDTR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) INTERCEPT_LOAD_LDTR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) INTERCEPT_LOAD_TR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) INTERCEPT_RDTSC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) INTERCEPT_RDPMC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) INTERCEPT_PUSHF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) INTERCEPT_POPF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) INTERCEPT_CPUID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) INTERCEPT_RSM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) INTERCEPT_IRET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) INTERCEPT_INTn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) INTERCEPT_INVD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) INTERCEPT_PAUSE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) INTERCEPT_HLT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) INTERCEPT_INVLPG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) INTERCEPT_INVLPGA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) INTERCEPT_IOIO_PROT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) INTERCEPT_MSR_PROT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) INTERCEPT_TASK_SWITCH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) INTERCEPT_FERR_FREEZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) INTERCEPT_SHUTDOWN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) /* Byte offset 010h (word 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) INTERCEPT_VMRUN = 128,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) INTERCEPT_VMMCALL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) INTERCEPT_VMLOAD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) INTERCEPT_VMSAVE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) INTERCEPT_STGI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) INTERCEPT_CLGI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) INTERCEPT_SKINIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) INTERCEPT_RDTSCP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) INTERCEPT_ICEBP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) INTERCEPT_WBINVD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) INTERCEPT_MONITOR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) INTERCEPT_MWAIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) INTERCEPT_MWAIT_COND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) INTERCEPT_XSETBV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) INTERCEPT_RDPRU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) /* Byte offset 014h (word 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) INTERCEPT_INVLPGB = 160,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) INTERCEPT_INVLPGB_ILLEGAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) INTERCEPT_INVPCID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) INTERCEPT_MCOMMIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) INTERCEPT_TLBSYNC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) struct __attribute__ ((__packed__)) vmcb_control_area {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) u32 intercepts[MAX_INTERCEPT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) u32 reserved_1[15 - MAX_INTERCEPT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) u16 pause_filter_thresh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) u16 pause_filter_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) u64 iopm_base_pa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) u64 msrpm_base_pa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) u64 tsc_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) u32 asid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) u8 tlb_ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) u8 reserved_2[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) u32 int_ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) u32 int_vector;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) u32 int_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) u8 reserved_3[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) u32 exit_code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) u32 exit_code_hi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) u64 exit_info_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) u64 exit_info_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) u32 exit_int_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) u32 exit_int_info_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) u64 nested_ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) u64 avic_vapic_bar;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) u8 reserved_4[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) u32 event_inj;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) u32 event_inj_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) u64 nested_cr3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) u64 virt_ext;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) u32 clean;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) u32 reserved_5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) u64 next_rip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) u8 insn_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) u8 insn_bytes[15];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) u64 avic_backing_page; /* Offset 0xe0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) u8 reserved_6[8]; /* Offset 0xe8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) u64 avic_logical_id; /* Offset 0xf0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) u64 avic_physical_id; /* Offset 0xf8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define TLB_CONTROL_DO_NOTHING 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define TLB_CONTROL_FLUSH_ALL_ASID 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define TLB_CONTROL_FLUSH_ASID 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define TLB_CONTROL_FLUSH_ASID_LOCAL 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define V_TPR_MASK 0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define V_IRQ_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define V_IRQ_MASK (1 << V_IRQ_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define V_GIF_SHIFT 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define V_GIF_MASK (1 << V_GIF_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define V_INTR_PRIO_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define V_INTR_PRIO_MASK (0x0f << V_INTR_PRIO_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define V_IGN_TPR_SHIFT 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define V_IGN_TPR_MASK (1 << V_IGN_TPR_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define V_IRQ_INJECTION_BITS_MASK (V_IRQ_MASK | V_INTR_PRIO_MASK | V_IGN_TPR_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define V_INTR_MASKING_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define V_INTR_MASKING_MASK (1 << V_INTR_MASKING_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define V_GIF_ENABLE_SHIFT 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define V_GIF_ENABLE_MASK (1 << V_GIF_ENABLE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define AVIC_ENABLE_SHIFT 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define AVIC_ENABLE_MASK (1 << AVIC_ENABLE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define LBR_CTL_ENABLE_MASK BIT_ULL(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define VIRTUAL_VMLOAD_VMSAVE_ENABLE_MASK BIT_ULL(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define SVM_INTERRUPT_SHADOW_MASK 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define SVM_IOIO_STR_SHIFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define SVM_IOIO_REP_SHIFT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define SVM_IOIO_SIZE_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define SVM_IOIO_ASIZE_SHIFT 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define SVM_IOIO_TYPE_MASK 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define SVM_IOIO_STR_MASK (1 << SVM_IOIO_STR_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define SVM_IOIO_REP_MASK (1 << SVM_IOIO_REP_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define SVM_IOIO_SIZE_MASK (7 << SVM_IOIO_SIZE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define SVM_IOIO_ASIZE_MASK (7 << SVM_IOIO_ASIZE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define SVM_VM_CR_VALID_MASK 0x001fULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define SVM_VM_CR_SVM_LOCK_MASK 0x0008ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define SVM_VM_CR_SVM_DIS_MASK 0x0010ULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define SVM_NESTED_CTL_NP_ENABLE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define SVM_NESTED_CTL_SEV_ENABLE BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) struct vmcb_seg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) u16 selector;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) u16 attrib;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) u32 limit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) u64 base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) struct vmcb_save_area {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) struct vmcb_seg es;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) struct vmcb_seg cs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) struct vmcb_seg ss;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) struct vmcb_seg ds;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) struct vmcb_seg fs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) struct vmcb_seg gs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) struct vmcb_seg gdtr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) struct vmcb_seg ldtr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) struct vmcb_seg idtr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) struct vmcb_seg tr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) u8 reserved_1[43];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) u8 cpl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) u8 reserved_2[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) u64 efer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) u8 reserved_3[112];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) u64 cr4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) u64 cr3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) u64 cr0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) u64 dr7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) u64 dr6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) u64 rflags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) u64 rip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) u8 reserved_4[88];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) u64 rsp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) u8 reserved_5[24];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) u64 rax;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) u64 star;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) u64 lstar;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) u64 cstar;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) u64 sfmask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) u64 kernel_gs_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) u64 sysenter_cs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) u64 sysenter_esp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) u64 sysenter_eip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) u64 cr2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) u8 reserved_6[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) u64 g_pat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) u64 dbgctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) u64 br_from;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) u64 br_to;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) u64 last_excp_from;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) u64 last_excp_to;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) * The following part of the save area is valid only for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) * SEV-ES guests when referenced through the GHCB.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) u8 reserved_7[104];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) u64 reserved_8; /* rax already available at 0x01f8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) u64 rcx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) u64 rdx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) u64 rbx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) u64 reserved_9; /* rsp already available at 0x01d8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) u64 rbp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) u64 rsi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) u64 rdi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) u64 r8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) u64 r9;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) u64 r10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) u64 r11;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) u64 r12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) u64 r13;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) u64 r14;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) u64 r15;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) u8 reserved_10[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) u64 sw_exit_code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) u64 sw_exit_info_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) u64 sw_exit_info_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) u64 sw_scratch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) u8 reserved_11[56];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) u64 xcr0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) u8 valid_bitmap[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) u64 x87_state_gpa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) struct ghcb {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) struct vmcb_save_area save;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) u8 reserved_save[2048 - sizeof(struct vmcb_save_area)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) u8 shared_buffer[2032];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) u8 reserved_1[10];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) u16 protocol_version; /* negotiated SEV-ES/GHCB protocol version */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) u32 ghcb_usage;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define EXPECTED_VMCB_SAVE_AREA_SIZE 1032
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define EXPECTED_VMCB_CONTROL_AREA_SIZE 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define EXPECTED_GHCB_SIZE PAGE_SIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) static inline void __unused_size_checks(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) BUILD_BUG_ON(sizeof(struct vmcb_save_area) != EXPECTED_VMCB_SAVE_AREA_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) BUILD_BUG_ON(sizeof(struct vmcb_control_area) != EXPECTED_VMCB_CONTROL_AREA_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) BUILD_BUG_ON(sizeof(struct ghcb) != EXPECTED_GHCB_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) struct vmcb {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) struct vmcb_control_area control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) u8 reserved_control[1024 - sizeof(struct vmcb_control_area)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) struct vmcb_save_area save;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) #define SVM_CPUID_FUNC 0x8000000a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) #define SVM_VM_CR_SVM_DISABLE 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #define SVM_SELECTOR_S_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) #define SVM_SELECTOR_DPL_SHIFT 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #define SVM_SELECTOR_P_SHIFT 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #define SVM_SELECTOR_AVL_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #define SVM_SELECTOR_L_SHIFT 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) #define SVM_SELECTOR_DB_SHIFT 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #define SVM_SELECTOR_G_SHIFT 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) #define SVM_SELECTOR_TYPE_MASK (0xf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) #define SVM_SELECTOR_S_MASK (1 << SVM_SELECTOR_S_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) #define SVM_SELECTOR_DPL_MASK (3 << SVM_SELECTOR_DPL_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #define SVM_SELECTOR_P_MASK (1 << SVM_SELECTOR_P_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #define SVM_SELECTOR_AVL_MASK (1 << SVM_SELECTOR_AVL_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #define SVM_SELECTOR_L_MASK (1 << SVM_SELECTOR_L_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #define SVM_SELECTOR_DB_MASK (1 << SVM_SELECTOR_DB_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #define SVM_SELECTOR_G_MASK (1 << SVM_SELECTOR_G_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #define SVM_SELECTOR_WRITE_MASK (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #define SVM_SELECTOR_READ_MASK SVM_SELECTOR_WRITE_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) #define SVM_SELECTOR_CODE_MASK (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) #define SVM_EVTINJ_VEC_MASK 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) #define SVM_EVTINJ_TYPE_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #define SVM_EVTINJ_TYPE_MASK (7 << SVM_EVTINJ_TYPE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #define SVM_EVTINJ_TYPE_INTR (0 << SVM_EVTINJ_TYPE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) #define SVM_EVTINJ_TYPE_NMI (2 << SVM_EVTINJ_TYPE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) #define SVM_EVTINJ_TYPE_EXEPT (3 << SVM_EVTINJ_TYPE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) #define SVM_EVTINJ_TYPE_SOFT (4 << SVM_EVTINJ_TYPE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) #define SVM_EVTINJ_VALID (1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) #define SVM_EVTINJ_VALID_ERR (1 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) #define SVM_EXITINTINFO_VEC_MASK SVM_EVTINJ_VEC_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) #define SVM_EXITINTINFO_TYPE_MASK SVM_EVTINJ_TYPE_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) #define SVM_EXITINTINFO_TYPE_INTR SVM_EVTINJ_TYPE_INTR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) #define SVM_EXITINTINFO_TYPE_NMI SVM_EVTINJ_TYPE_NMI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) #define SVM_EXITINTINFO_TYPE_EXEPT SVM_EVTINJ_TYPE_EXEPT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) #define SVM_EXITINTINFO_TYPE_SOFT SVM_EVTINJ_TYPE_SOFT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) #define SVM_EXITINTINFO_VALID SVM_EVTINJ_VALID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) #define SVM_EXITINTINFO_VALID_ERR SVM_EVTINJ_VALID_ERR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) #define SVM_EXITINFOSHIFT_TS_REASON_IRET 36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) #define SVM_EXITINFOSHIFT_TS_REASON_JMP 38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) #define SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE 44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) #define SVM_EXITINFO_REG_MASK 0x0F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) #define SVM_CR0_SELECTIVE_MASK (X86_CR0_TS | X86_CR0_MP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) /* GHCB Accessor functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) #define GHCB_BITMAP_IDX(field) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) (offsetof(struct vmcb_save_area, field) / sizeof(u64))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) #define DEFINE_GHCB_ACCESSORS(field) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) static inline bool ghcb_##field##_is_valid(const struct ghcb *ghcb) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) return test_bit(GHCB_BITMAP_IDX(field), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) (unsigned long *)&ghcb->save.valid_bitmap); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) } \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) static inline void ghcb_set_##field(struct ghcb *ghcb, u64 value) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) __set_bit(GHCB_BITMAP_IDX(field), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) (unsigned long *)&ghcb->save.valid_bitmap); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) ghcb->save.field = value; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) DEFINE_GHCB_ACCESSORS(cpl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) DEFINE_GHCB_ACCESSORS(rip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) DEFINE_GHCB_ACCESSORS(rsp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) DEFINE_GHCB_ACCESSORS(rax)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) DEFINE_GHCB_ACCESSORS(rcx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) DEFINE_GHCB_ACCESSORS(rdx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) DEFINE_GHCB_ACCESSORS(rbx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) DEFINE_GHCB_ACCESSORS(rbp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) DEFINE_GHCB_ACCESSORS(rsi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) DEFINE_GHCB_ACCESSORS(rdi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) DEFINE_GHCB_ACCESSORS(r8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) DEFINE_GHCB_ACCESSORS(r9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) DEFINE_GHCB_ACCESSORS(r10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) DEFINE_GHCB_ACCESSORS(r11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) DEFINE_GHCB_ACCESSORS(r12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) DEFINE_GHCB_ACCESSORS(r13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) DEFINE_GHCB_ACCESSORS(r14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) DEFINE_GHCB_ACCESSORS(r15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) DEFINE_GHCB_ACCESSORS(sw_exit_code)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) DEFINE_GHCB_ACCESSORS(sw_exit_info_1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) DEFINE_GHCB_ACCESSORS(sw_exit_info_2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) DEFINE_GHCB_ACCESSORS(sw_scratch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) DEFINE_GHCB_ACCESSORS(xcr0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags