^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) #ifndef _ASM_X86_SPECCTRL_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) #define _ASM_X86_SPECCTRL_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #include <linux/thread_info.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <asm/nospec-branch.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * On VMENTER we must preserve whatever view of the SPEC_CTRL MSR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * the guest has, while on VMEXIT we restore the host view. This
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * would be easier if SPEC_CTRL were architecturally maskable or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * shadowable for guests but this is not (currently) the case.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * Takes the guest view of SPEC_CTRL MSR as a parameter and also
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * the guest's version of VIRT_SPEC_CTRL, if emulated.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) extern void x86_virt_spec_ctrl(u64 guest_spec_ctrl, u64 guest_virt_spec_ctrl, bool guest);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * x86_spec_ctrl_set_guest - Set speculation control registers for the guest
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * @guest_spec_ctrl: The guest content of MSR_SPEC_CTRL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * @guest_virt_spec_ctrl: The guest controlled bits of MSR_VIRT_SPEC_CTRL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * (may get translated to MSR_AMD64_LS_CFG bits)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * Avoids writing to the MSR if the content/bits are the same
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) static inline
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) void x86_spec_ctrl_set_guest(u64 guest_spec_ctrl, u64 guest_virt_spec_ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) x86_virt_spec_ctrl(guest_spec_ctrl, guest_virt_spec_ctrl, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * x86_spec_ctrl_restore_host - Restore host speculation control registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * @guest_spec_ctrl: The guest content of MSR_SPEC_CTRL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * @guest_virt_spec_ctrl: The guest controlled bits of MSR_VIRT_SPEC_CTRL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * (may get translated to MSR_AMD64_LS_CFG bits)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * Avoids writing to the MSR if the content/bits are the same
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) static inline
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) void x86_spec_ctrl_restore_host(u64 guest_spec_ctrl, u64 guest_virt_spec_ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) x86_virt_spec_ctrl(guest_spec_ctrl, guest_virt_spec_ctrl, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) /* AMD specific Speculative Store Bypass MSR data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) extern u64 x86_amd_ls_cfg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) extern u64 x86_amd_ls_cfg_ssbd_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) static inline u64 ssbd_tif_to_spec_ctrl(u64 tifn)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) BUILD_BUG_ON(TIF_SSBD < SPEC_CTRL_SSBD_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) return (tifn & _TIF_SSBD) >> (TIF_SSBD - SPEC_CTRL_SSBD_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) static inline u64 stibp_tif_to_spec_ctrl(u64 tifn)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) BUILD_BUG_ON(TIF_SPEC_IB < SPEC_CTRL_STIBP_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) return (tifn & _TIF_SPEC_IB) >> (TIF_SPEC_IB - SPEC_CTRL_STIBP_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) static inline unsigned long ssbd_spec_ctrl_to_tif(u64 spec_ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) BUILD_BUG_ON(TIF_SSBD < SPEC_CTRL_SSBD_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) return (spec_ctrl & SPEC_CTRL_SSBD) << (TIF_SSBD - SPEC_CTRL_SSBD_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) static inline unsigned long stibp_spec_ctrl_to_tif(u64 spec_ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) BUILD_BUG_ON(TIF_SPEC_IB < SPEC_CTRL_STIBP_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) return (spec_ctrl & SPEC_CTRL_STIBP) << (TIF_SPEC_IB - SPEC_CTRL_STIBP_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) static inline u64 ssbd_tif_to_amd_ls_cfg(u64 tifn)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) return (tifn & _TIF_SSBD) ? x86_amd_ls_cfg_ssbd_mask : 0ULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #ifdef CONFIG_SMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) extern void speculative_store_bypass_ht_init(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) static inline void speculative_store_bypass_ht_init(void) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) extern void speculation_ctrl_update(unsigned long tif);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) extern void speculation_ctrl_update_current(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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