^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) #ifndef _ASM_X86_PCI_DIRECT_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) #define _ASM_X86_PCI_DIRECT_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) /* Direct PCI access. This is used for PCI accesses in early boot before
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) the PCI subsystem works. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) extern u32 read_pci_config(u8 bus, u8 slot, u8 func, u8 offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) extern u8 read_pci_config_byte(u8 bus, u8 slot, u8 func, u8 offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) extern u16 read_pci_config_16(u8 bus, u8 slot, u8 func, u8 offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) extern void write_pci_config(u8 bus, u8 slot, u8 func, u8 offset, u32 val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) extern void write_pci_config_byte(u8 bus, u8 slot, u8 func, u8 offset, u8 val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) extern void write_pci_config_16(u8 bus, u8 slot, u8 func, u8 offset, u16 val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) extern int early_pci_allowed(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #endif /* _ASM_X86_PCI_DIRECT_H */