Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) #ifndef _ASM_X86_MSR_INDEX_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3) #define _ASM_X86_MSR_INDEX_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) #include <linux/bits.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * CPU model specific register (MSR) numbers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  * Do not add new entries to this file unless the definitions are shared
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  * between multiple compilation units.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) /* x86-64 specific MSRs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #define MSR_EFER		0xc0000080 /* extended feature register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #define MSR_STAR		0xc0000081 /* legacy mode SYSCALL target */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #define MSR_LSTAR		0xc0000082 /* long mode SYSCALL target */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define MSR_CSTAR		0xc0000083 /* compat mode SYSCALL target */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define MSR_SYSCALL_MASK	0xc0000084 /* EFLAGS mask for syscall */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define MSR_FS_BASE		0xc0000100 /* 64bit FS base */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define MSR_GS_BASE		0xc0000101 /* 64bit GS base */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define MSR_KERNEL_GS_BASE	0xc0000102 /* SwapGS GS shadow */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define MSR_TSC_AUX		0xc0000103 /* Auxiliary TSC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) /* EFER bits: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define _EFER_SCE		0  /* SYSCALL/SYSRET */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define _EFER_LME		8  /* Long mode enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define _EFER_LMA		10 /* Long mode active (read-only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define _EFER_NX		11 /* No execute enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define _EFER_SVME		12 /* Enable virtualization */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define _EFER_LMSLE		13 /* Long Mode Segment Limit Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define _EFER_FFXSR		14 /* Enable Fast FXSAVE/FXRSTOR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define EFER_SCE		(1<<_EFER_SCE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define EFER_LME		(1<<_EFER_LME)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define EFER_LMA		(1<<_EFER_LMA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define EFER_NX			(1<<_EFER_NX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define EFER_SVME		(1<<_EFER_SVME)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define EFER_LMSLE		(1<<_EFER_LMSLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define EFER_FFXSR		(1<<_EFER_FFXSR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) /* Intel MSRs. Some also available on other CPUs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define MSR_TEST_CTRL				0x00000033
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define MSR_TEST_CTRL_SPLIT_LOCK_DETECT_BIT	29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define MSR_TEST_CTRL_SPLIT_LOCK_DETECT		BIT(MSR_TEST_CTRL_SPLIT_LOCK_DETECT_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define MSR_IA32_SPEC_CTRL		0x00000048 /* Speculation Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define SPEC_CTRL_IBRS			BIT(0)	   /* Indirect Branch Restricted Speculation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define SPEC_CTRL_STIBP_SHIFT		1	   /* Single Thread Indirect Branch Predictor (STIBP) bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define SPEC_CTRL_STIBP			BIT(SPEC_CTRL_STIBP_SHIFT)	/* STIBP mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define SPEC_CTRL_SSBD_SHIFT		2	   /* Speculative Store Bypass Disable bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define SPEC_CTRL_SSBD			BIT(SPEC_CTRL_SSBD_SHIFT)	/* Speculative Store Bypass Disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define MSR_IA32_PRED_CMD		0x00000049 /* Prediction Command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define PRED_CMD_IBPB			BIT(0)	   /* Indirect Branch Prediction Barrier */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define MSR_PPIN_CTL			0x0000004e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define MSR_PPIN			0x0000004f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define MSR_IA32_PERFCTR0		0x000000c1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define MSR_IA32_PERFCTR1		0x000000c2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define MSR_FSB_FREQ			0x000000cd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define MSR_PLATFORM_INFO		0x000000ce
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define MSR_PLATFORM_INFO_CPUID_FAULT_BIT	31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define MSR_PLATFORM_INFO_CPUID_FAULT		BIT_ULL(MSR_PLATFORM_INFO_CPUID_FAULT_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define MSR_IA32_UMWAIT_CONTROL			0xe1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define MSR_IA32_UMWAIT_CONTROL_C02_DISABLE	BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define MSR_IA32_UMWAIT_CONTROL_RESERVED	BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72)  * The time field is bit[31:2], but representing a 32bit value with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73)  * bit[1:0] zero.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define MSR_IA32_UMWAIT_CONTROL_TIME_MASK	(~0x03U)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) /* Abbreviated from Intel SDM name IA32_CORE_CAPABILITIES */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #define MSR_IA32_CORE_CAPS			  0x000000cf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #define MSR_IA32_CORE_CAPS_SPLIT_LOCK_DETECT_BIT  5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) #define MSR_IA32_CORE_CAPS_SPLIT_LOCK_DETECT	  BIT(MSR_IA32_CORE_CAPS_SPLIT_LOCK_DETECT_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define MSR_PKG_CST_CONFIG_CONTROL	0x000000e2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #define NHM_C3_AUTO_DEMOTE		(1UL << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) #define NHM_C1_AUTO_DEMOTE		(1UL << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) #define ATM_LNC_C6_AUTO_DEMOTE		(1UL << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #define SNB_C3_AUTO_UNDEMOTE		(1UL << 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) #define SNB_C1_AUTO_UNDEMOTE		(1UL << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) #define MSR_MTRRcap			0x000000fe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) #define MSR_IA32_ARCH_CAPABILITIES	0x0000010a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) #define ARCH_CAP_RDCL_NO		BIT(0)	/* Not susceptible to Meltdown */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) #define ARCH_CAP_IBRS_ALL		BIT(1)	/* Enhanced IBRS support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) #define ARCH_CAP_SKIP_VMENTRY_L1DFLUSH	BIT(3)	/* Skip L1D flush on vmentry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) #define ARCH_CAP_SSB_NO			BIT(4)	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 						 * Not susceptible to Speculative Store Bypass
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 						 * attack, so no Speculative Store Bypass
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 						 * control required.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 						 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define ARCH_CAP_MDS_NO			BIT(5)   /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 						  * Not susceptible to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 						  * Microarchitectural Data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 						  * Sampling (MDS) vulnerabilities.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 						  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define ARCH_CAP_PSCHANGE_MC_NO		BIT(6)	 /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 						  * The processor is not susceptible to a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 						  * machine check error due to modifying the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 						  * code page size along with either the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 						  * physical address or cache type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 						  * without TLB invalidation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 						  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define ARCH_CAP_TSX_CTRL_MSR		BIT(7)	/* MSR for TSX control is available. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define ARCH_CAP_TAA_NO			BIT(8)	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 						 * Not susceptible to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 						 * TSX Async Abort (TAA) vulnerabilities.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 						 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define MSR_IA32_FLUSH_CMD		0x0000010b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define L1D_FLUSH			BIT(0)	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 						 * Writeback and invalidate the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 						 * L1 data cache.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 						 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define MSR_IA32_BBL_CR_CTL		0x00000119
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define MSR_IA32_BBL_CR_CTL3		0x0000011e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define MSR_IA32_TSX_CTRL		0x00000122
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define TSX_CTRL_RTM_DISABLE		BIT(0)	/* Disable RTM feature */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define TSX_CTRL_CPUID_CLEAR		BIT(1)	/* Disable TSX enumeration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) /* SRBDS support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define MSR_IA32_MCU_OPT_CTRL		0x00000123
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define RNGDS_MITG_DIS			BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define MSR_IA32_SYSENTER_CS		0x00000174
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define MSR_IA32_SYSENTER_ESP		0x00000175
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define MSR_IA32_SYSENTER_EIP		0x00000176
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define MSR_IA32_MCG_CAP		0x00000179
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define MSR_IA32_MCG_STATUS		0x0000017a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define MSR_IA32_MCG_CTL		0x0000017b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define MSR_IA32_MCG_EXT_CTL		0x000004d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define MSR_OFFCORE_RSP_0		0x000001a6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define MSR_OFFCORE_RSP_1		0x000001a7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define MSR_TURBO_RATIO_LIMIT		0x000001ad
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define MSR_TURBO_RATIO_LIMIT1		0x000001ae
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define MSR_TURBO_RATIO_LIMIT2		0x000001af
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define MSR_LBR_SELECT			0x000001c8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define MSR_LBR_TOS			0x000001c9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define MSR_IA32_POWER_CTL		0x000001fc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define MSR_IA32_POWER_CTL_BIT_EE	19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define MSR_LBR_NHM_FROM		0x00000680
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define MSR_LBR_NHM_TO			0x000006c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define MSR_LBR_CORE_FROM		0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define MSR_LBR_CORE_TO			0x00000060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define MSR_LBR_INFO_0			0x00000dc0 /* ... 0xddf for _31 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define LBR_INFO_MISPRED		BIT_ULL(63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define LBR_INFO_IN_TX			BIT_ULL(62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define LBR_INFO_ABORT			BIT_ULL(61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define LBR_INFO_CYC_CNT_VALID		BIT_ULL(60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define LBR_INFO_CYCLES			0xffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define LBR_INFO_BR_TYPE_OFFSET		56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define LBR_INFO_BR_TYPE		(0xfull << LBR_INFO_BR_TYPE_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define MSR_ARCH_LBR_CTL		0x000014ce
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define ARCH_LBR_CTL_LBREN		BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define ARCH_LBR_CTL_CPL_OFFSET		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define ARCH_LBR_CTL_CPL		(0x3ull << ARCH_LBR_CTL_CPL_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define ARCH_LBR_CTL_STACK_OFFSET	3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define ARCH_LBR_CTL_STACK		(0x1ull << ARCH_LBR_CTL_STACK_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define ARCH_LBR_CTL_FILTER_OFFSET	16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define ARCH_LBR_CTL_FILTER		(0x7full << ARCH_LBR_CTL_FILTER_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define MSR_ARCH_LBR_DEPTH		0x000014cf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define MSR_ARCH_LBR_FROM_0		0x00001500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define MSR_ARCH_LBR_TO_0		0x00001600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define MSR_ARCH_LBR_INFO_0		0x00001200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define MSR_IA32_PEBS_ENABLE		0x000003f1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define MSR_PEBS_DATA_CFG		0x000003f2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define MSR_IA32_DS_AREA		0x00000600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define MSR_IA32_PERF_CAPABILITIES	0x00000345
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define MSR_PEBS_LD_LAT_THRESHOLD	0x000003f6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define MSR_IA32_RTIT_CTL		0x00000570
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define RTIT_CTL_TRACEEN		BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define RTIT_CTL_CYCLEACC		BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define RTIT_CTL_OS			BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define RTIT_CTL_USR			BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define RTIT_CTL_PWR_EVT_EN		BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define RTIT_CTL_FUP_ON_PTW		BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define RTIT_CTL_FABRIC_EN		BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define RTIT_CTL_CR3EN			BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define RTIT_CTL_TOPA			BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define RTIT_CTL_MTC_EN			BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define RTIT_CTL_TSC_EN			BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define RTIT_CTL_DISRETC		BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define RTIT_CTL_PTW_EN			BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define RTIT_CTL_BRANCH_EN		BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define RTIT_CTL_MTC_RANGE_OFFSET	14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define RTIT_CTL_MTC_RANGE		(0x0full << RTIT_CTL_MTC_RANGE_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define RTIT_CTL_CYC_THRESH_OFFSET	19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define RTIT_CTL_CYC_THRESH		(0x0full << RTIT_CTL_CYC_THRESH_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define RTIT_CTL_PSB_FREQ_OFFSET	24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define RTIT_CTL_PSB_FREQ		(0x0full << RTIT_CTL_PSB_FREQ_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define RTIT_CTL_ADDR0_OFFSET		32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define RTIT_CTL_ADDR0			(0x0full << RTIT_CTL_ADDR0_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define RTIT_CTL_ADDR1_OFFSET		36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define RTIT_CTL_ADDR1			(0x0full << RTIT_CTL_ADDR1_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define RTIT_CTL_ADDR2_OFFSET		40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define RTIT_CTL_ADDR2			(0x0full << RTIT_CTL_ADDR2_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define RTIT_CTL_ADDR3_OFFSET		44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define RTIT_CTL_ADDR3			(0x0full << RTIT_CTL_ADDR3_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define MSR_IA32_RTIT_STATUS		0x00000571
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define RTIT_STATUS_FILTEREN		BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define RTIT_STATUS_CONTEXTEN		BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define RTIT_STATUS_TRIGGEREN		BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define RTIT_STATUS_BUFFOVF		BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define RTIT_STATUS_ERROR		BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define RTIT_STATUS_STOPPED		BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define RTIT_STATUS_BYTECNT_OFFSET	32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define RTIT_STATUS_BYTECNT		(0x1ffffull << RTIT_STATUS_BYTECNT_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define MSR_IA32_RTIT_ADDR0_A		0x00000580
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define MSR_IA32_RTIT_ADDR0_B		0x00000581
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define MSR_IA32_RTIT_ADDR1_A		0x00000582
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define MSR_IA32_RTIT_ADDR1_B		0x00000583
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define MSR_IA32_RTIT_ADDR2_A		0x00000584
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define MSR_IA32_RTIT_ADDR2_B		0x00000585
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define MSR_IA32_RTIT_ADDR3_A		0x00000586
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define MSR_IA32_RTIT_ADDR3_B		0x00000587
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define MSR_IA32_RTIT_CR3_MATCH		0x00000572
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define MSR_IA32_RTIT_OUTPUT_BASE	0x00000560
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define MSR_IA32_RTIT_OUTPUT_MASK	0x00000561
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define MSR_MTRRfix64K_00000		0x00000250
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define MSR_MTRRfix16K_80000		0x00000258
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define MSR_MTRRfix16K_A0000		0x00000259
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define MSR_MTRRfix4K_C0000		0x00000268
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define MSR_MTRRfix4K_C8000		0x00000269
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define MSR_MTRRfix4K_D0000		0x0000026a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define MSR_MTRRfix4K_D8000		0x0000026b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define MSR_MTRRfix4K_E0000		0x0000026c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define MSR_MTRRfix4K_E8000		0x0000026d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define MSR_MTRRfix4K_F0000		0x0000026e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define MSR_MTRRfix4K_F8000		0x0000026f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define MSR_MTRRdefType			0x000002ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define MSR_IA32_CR_PAT			0x00000277
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define MSR_IA32_DEBUGCTLMSR		0x000001d9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define MSR_IA32_LASTBRANCHFROMIP	0x000001db
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define MSR_IA32_LASTBRANCHTOIP		0x000001dc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define MSR_IA32_LASTINTFROMIP		0x000001dd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define MSR_IA32_LASTINTTOIP		0x000001de
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define MSR_IA32_PASID			0x00000d93
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define MSR_IA32_PASID_VALID		BIT_ULL(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) /* DEBUGCTLMSR bits (others vary by model): */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define DEBUGCTLMSR_LBR			(1UL <<  0) /* last branch recording */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define DEBUGCTLMSR_BTF_SHIFT		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define DEBUGCTLMSR_BTF			(1UL <<  1) /* single-step on branches */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define DEBUGCTLMSR_TR			(1UL <<  6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define DEBUGCTLMSR_BTS			(1UL <<  7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define DEBUGCTLMSR_BTINT		(1UL <<  8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define DEBUGCTLMSR_BTS_OFF_OS		(1UL <<  9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define DEBUGCTLMSR_BTS_OFF_USR		(1UL << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define DEBUGCTLMSR_FREEZE_LBRS_ON_PMI	(1UL << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define DEBUGCTLMSR_FREEZE_PERFMON_ON_PMI	(1UL << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define DEBUGCTLMSR_FREEZE_IN_SMM_BIT	14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define DEBUGCTLMSR_FREEZE_IN_SMM	(1UL << DEBUGCTLMSR_FREEZE_IN_SMM_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define MSR_PEBS_FRONTEND		0x000003f7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define MSR_IA32_MC0_CTL		0x00000400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define MSR_IA32_MC0_STATUS		0x00000401
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define MSR_IA32_MC0_ADDR		0x00000402
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define MSR_IA32_MC0_MISC		0x00000403
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) /* C-state Residency Counters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define MSR_PKG_C3_RESIDENCY		0x000003f8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define MSR_PKG_C6_RESIDENCY		0x000003f9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define MSR_ATOM_PKG_C6_RESIDENCY	0x000003fa
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define MSR_PKG_C7_RESIDENCY		0x000003fa
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define MSR_CORE_C3_RESIDENCY		0x000003fc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define MSR_CORE_C6_RESIDENCY		0x000003fd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define MSR_CORE_C7_RESIDENCY		0x000003fe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define MSR_KNL_CORE_C6_RESIDENCY	0x000003ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define MSR_PKG_C2_RESIDENCY		0x0000060d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define MSR_PKG_C8_RESIDENCY		0x00000630
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define MSR_PKG_C9_RESIDENCY		0x00000631
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define MSR_PKG_C10_RESIDENCY		0x00000632
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) /* Interrupt Response Limit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define MSR_PKGC3_IRTL			0x0000060a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define MSR_PKGC6_IRTL			0x0000060b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #define MSR_PKGC7_IRTL			0x0000060c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define MSR_PKGC8_IRTL			0x00000633
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #define MSR_PKGC9_IRTL			0x00000634
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #define MSR_PKGC10_IRTL			0x00000635
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) /* Run Time Average Power Limiting (RAPL) Interface */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define MSR_RAPL_POWER_UNIT		0x00000606
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #define MSR_PKG_POWER_LIMIT		0x00000610
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define MSR_PKG_ENERGY_STATUS		0x00000611
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #define MSR_PKG_PERF_STATUS		0x00000613
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) #define MSR_PKG_POWER_INFO		0x00000614
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) #define MSR_DRAM_POWER_LIMIT		0x00000618
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) #define MSR_DRAM_ENERGY_STATUS		0x00000619
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) #define MSR_DRAM_PERF_STATUS		0x0000061b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #define MSR_DRAM_POWER_INFO		0x0000061c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) #define MSR_PP0_POWER_LIMIT		0x00000638
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #define MSR_PP0_ENERGY_STATUS		0x00000639
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #define MSR_PP0_POLICY			0x0000063a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #define MSR_PP0_PERF_STATUS		0x0000063b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #define MSR_PP1_POWER_LIMIT		0x00000640
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) #define MSR_PP1_ENERGY_STATUS		0x00000641
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) #define MSR_PP1_POLICY			0x00000642
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) #define MSR_AMD_PKG_ENERGY_STATUS	0xc001029b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #define MSR_AMD_RAPL_POWER_UNIT		0xc0010299
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) /* Config TDP MSRs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #define MSR_CONFIG_TDP_NOMINAL		0x00000648
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #define MSR_CONFIG_TDP_LEVEL_1		0x00000649
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #define MSR_CONFIG_TDP_LEVEL_2		0x0000064A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #define MSR_CONFIG_TDP_CONTROL		0x0000064B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #define MSR_TURBO_ACTIVATION_RATIO	0x0000064C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #define MSR_PLATFORM_ENERGY_STATUS	0x0000064D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #define MSR_PKG_WEIGHTED_CORE_C0_RES	0x00000658
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) #define MSR_PKG_ANY_CORE_C0_RES		0x00000659
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #define MSR_PKG_ANY_GFXE_C0_RES		0x0000065A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) #define MSR_PKG_BOTH_CORE_GFXE_C0_RES	0x0000065B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) #define MSR_CORE_C1_RES			0x00000660
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) #define MSR_MODULE_C6_RES_MS		0x00000664
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) #define MSR_CC6_DEMOTION_POLICY_CONFIG	0x00000668
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) #define MSR_MC6_DEMOTION_POLICY_CONFIG	0x00000669
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) #define MSR_ATOM_CORE_RATIOS		0x0000066a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) #define MSR_ATOM_CORE_VIDS		0x0000066b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) #define MSR_ATOM_CORE_TURBO_RATIOS	0x0000066c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) #define MSR_ATOM_CORE_TURBO_VIDS	0x0000066d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) #define MSR_CORE_PERF_LIMIT_REASONS	0x00000690
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) #define MSR_GFX_PERF_LIMIT_REASONS	0x000006B0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) #define MSR_RING_PERF_LIMIT_REASONS	0x000006B1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) /* Hardware P state interface */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) #define MSR_PPERF			0x0000064e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) #define MSR_PERF_LIMIT_REASONS		0x0000064f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) #define MSR_PM_ENABLE			0x00000770
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) #define MSR_HWP_CAPABILITIES		0x00000771
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) #define MSR_HWP_REQUEST_PKG		0x00000772
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) #define MSR_HWP_INTERRUPT		0x00000773
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) #define MSR_HWP_REQUEST 		0x00000774
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) #define MSR_HWP_STATUS			0x00000777
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) /* CPUID.6.EAX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) #define HWP_BASE_BIT			(1<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) #define HWP_NOTIFICATIONS_BIT		(1<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) #define HWP_ACTIVITY_WINDOW_BIT		(1<<9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) #define HWP_ENERGY_PERF_PREFERENCE_BIT	(1<<10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) #define HWP_PACKAGE_LEVEL_REQUEST_BIT	(1<<11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) /* IA32_HWP_CAPABILITIES */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) #define HWP_HIGHEST_PERF(x)		(((x) >> 0) & 0xff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) #define HWP_GUARANTEED_PERF(x)		(((x) >> 8) & 0xff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) #define HWP_MOSTEFFICIENT_PERF(x)	(((x) >> 16) & 0xff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) #define HWP_LOWEST_PERF(x)		(((x) >> 24) & 0xff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) /* IA32_HWP_REQUEST */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) #define HWP_MIN_PERF(x) 		(x & 0xff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) #define HWP_MAX_PERF(x) 		((x & 0xff) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) #define HWP_DESIRED_PERF(x)		((x & 0xff) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) #define HWP_ENERGY_PERF_PREFERENCE(x)	(((unsigned long long) x & 0xff) << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) #define HWP_EPP_PERFORMANCE		0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) #define HWP_EPP_BALANCE_PERFORMANCE	0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) #define HWP_EPP_BALANCE_POWERSAVE	0xC0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) #define HWP_EPP_POWERSAVE		0xFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) #define HWP_ACTIVITY_WINDOW(x)		((unsigned long long)(x & 0xff3) << 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) #define HWP_PACKAGE_CONTROL(x)		((unsigned long long)(x & 0x1) << 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) /* IA32_HWP_STATUS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) #define HWP_GUARANTEED_CHANGE(x)	(x & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) #define HWP_EXCURSION_TO_MINIMUM(x)	(x & 0x4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) /* IA32_HWP_INTERRUPT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) #define HWP_CHANGE_TO_GUARANTEED_INT(x)	(x & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) #define HWP_EXCURSION_TO_MINIMUM_INT(x)	(x & 0x2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) #define MSR_AMD64_MC0_MASK		0xc0010044
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) #define MSR_IA32_MCx_CTL(x)		(MSR_IA32_MC0_CTL + 4*(x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) #define MSR_IA32_MCx_STATUS(x)		(MSR_IA32_MC0_STATUS + 4*(x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) #define MSR_IA32_MCx_ADDR(x)		(MSR_IA32_MC0_ADDR + 4*(x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) #define MSR_IA32_MCx_MISC(x)		(MSR_IA32_MC0_MISC + 4*(x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) #define MSR_AMD64_MCx_MASK(x)		(MSR_AMD64_MC0_MASK + (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) /* These are consecutive and not in the normal 4er MCE bank block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) #define MSR_IA32_MC0_CTL2		0x00000280
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) #define MSR_IA32_MCx_CTL2(x)		(MSR_IA32_MC0_CTL2 + (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) #define MSR_P6_PERFCTR0			0x000000c1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) #define MSR_P6_PERFCTR1			0x000000c2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) #define MSR_P6_EVNTSEL0			0x00000186
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) #define MSR_P6_EVNTSEL1			0x00000187
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) #define MSR_KNC_PERFCTR0               0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) #define MSR_KNC_PERFCTR1               0x00000021
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) #define MSR_KNC_EVNTSEL0               0x00000028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) #define MSR_KNC_EVNTSEL1               0x00000029
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) /* Alternative perfctr range with full access. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) #define MSR_IA32_PMC0			0x000004c1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) /* Auto-reload via MSR instead of DS area */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) #define MSR_RELOAD_PMC0			0x000014c1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) #define MSR_RELOAD_FIXED_CTR0		0x00001309
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)  * AMD64 MSRs. Not complete. See the architecture manual for a more
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)  * complete list.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) #define MSR_AMD64_PATCH_LEVEL		0x0000008b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) #define MSR_AMD64_TSC_RATIO		0xc0000104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) #define MSR_AMD64_NB_CFG		0xc001001f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) #define MSR_AMD64_PATCH_LOADER		0xc0010020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) #define MSR_AMD_PERF_CTL		0xc0010062
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) #define MSR_AMD_PERF_STATUS		0xc0010063
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) #define MSR_AMD_PSTATE_DEF_BASE		0xc0010064
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) #define MSR_AMD64_OSVW_ID_LENGTH	0xc0010140
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) #define MSR_AMD64_OSVW_STATUS		0xc0010141
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) #define MSR_AMD_PPIN_CTL		0xc00102f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) #define MSR_AMD_PPIN			0xc00102f1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) #define MSR_AMD64_CPUID_FN_1		0xc0011004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) #define MSR_AMD64_LS_CFG		0xc0011020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) #define MSR_AMD64_DC_CFG		0xc0011022
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) #define MSR_AMD64_BU_CFG2		0xc001102a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) #define MSR_AMD64_IBSFETCHCTL		0xc0011030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) #define MSR_AMD64_IBSFETCHLINAD		0xc0011031
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) #define MSR_AMD64_IBSFETCHPHYSAD	0xc0011032
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) #define MSR_AMD64_IBSFETCH_REG_COUNT	3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) #define MSR_AMD64_IBSFETCH_REG_MASK	((1UL<<MSR_AMD64_IBSFETCH_REG_COUNT)-1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) #define MSR_AMD64_IBSOPCTL		0xc0011033
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) #define MSR_AMD64_IBSOPRIP		0xc0011034
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) #define MSR_AMD64_IBSOPDATA		0xc0011035
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) #define MSR_AMD64_IBSOPDATA2		0xc0011036
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) #define MSR_AMD64_IBSOPDATA3		0xc0011037
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) #define MSR_AMD64_IBSDCLINAD		0xc0011038
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) #define MSR_AMD64_IBSDCPHYSAD		0xc0011039
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) #define MSR_AMD64_IBSOP_REG_COUNT	7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) #define MSR_AMD64_IBSOP_REG_MASK	((1UL<<MSR_AMD64_IBSOP_REG_COUNT)-1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) #define MSR_AMD64_IBSCTL		0xc001103a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) #define MSR_AMD64_IBSBRTARGET		0xc001103b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) #define MSR_AMD64_ICIBSEXTDCTL		0xc001103c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) #define MSR_AMD64_IBSOPDATA4		0xc001103d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) #define MSR_AMD64_IBS_REG_COUNT_MAX	8 /* includes MSR_AMD64_IBSBRTARGET */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) #define MSR_AMD64_SEV_ES_GHCB		0xc0010130
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) #define MSR_AMD64_SEV			0xc0010131
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) #define MSR_AMD64_SEV_ENABLED_BIT	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) #define MSR_AMD64_SEV_ES_ENABLED_BIT	1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) #define MSR_AMD64_SEV_ENABLED		BIT_ULL(MSR_AMD64_SEV_ENABLED_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) #define MSR_AMD64_SEV_ES_ENABLED	BIT_ULL(MSR_AMD64_SEV_ES_ENABLED_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) #define MSR_AMD64_VIRT_SPEC_CTRL	0xc001011f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) /* Fam 17h MSRs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) #define MSR_F17H_IRPERF			0xc00000e9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) /* Fam 16h MSRs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) #define MSR_F16H_L2I_PERF_CTL		0xc0010230
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) #define MSR_F16H_L2I_PERF_CTR		0xc0010231
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) #define MSR_F16H_DR1_ADDR_MASK		0xc0011019
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) #define MSR_F16H_DR2_ADDR_MASK		0xc001101a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) #define MSR_F16H_DR3_ADDR_MASK		0xc001101b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) #define MSR_F16H_DR0_ADDR_MASK		0xc0011027
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) /* Fam 15h MSRs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) #define MSR_F15H_CU_PWR_ACCUMULATOR     0xc001007a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) #define MSR_F15H_CU_MAX_PWR_ACCUMULATOR 0xc001007b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) #define MSR_F15H_PERF_CTL		0xc0010200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) #define MSR_F15H_PERF_CTL0		MSR_F15H_PERF_CTL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) #define MSR_F15H_PERF_CTL1		(MSR_F15H_PERF_CTL + 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) #define MSR_F15H_PERF_CTL2		(MSR_F15H_PERF_CTL + 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) #define MSR_F15H_PERF_CTL3		(MSR_F15H_PERF_CTL + 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) #define MSR_F15H_PERF_CTL4		(MSR_F15H_PERF_CTL + 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) #define MSR_F15H_PERF_CTL5		(MSR_F15H_PERF_CTL + 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) #define MSR_F15H_PERF_CTR		0xc0010201
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) #define MSR_F15H_PERF_CTR0		MSR_F15H_PERF_CTR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) #define MSR_F15H_PERF_CTR1		(MSR_F15H_PERF_CTR + 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) #define MSR_F15H_PERF_CTR2		(MSR_F15H_PERF_CTR + 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) #define MSR_F15H_PERF_CTR3		(MSR_F15H_PERF_CTR + 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) #define MSR_F15H_PERF_CTR4		(MSR_F15H_PERF_CTR + 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) #define MSR_F15H_PERF_CTR5		(MSR_F15H_PERF_CTR + 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) #define MSR_F15H_NB_PERF_CTL		0xc0010240
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) #define MSR_F15H_NB_PERF_CTR		0xc0010241
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) #define MSR_F15H_PTSC			0xc0010280
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) #define MSR_F15H_IC_CFG			0xc0011021
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) #define MSR_F15H_EX_CFG			0xc001102c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) /* Fam 10h MSRs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) #define MSR_FAM10H_MMIO_CONF_BASE	0xc0010058
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) #define FAM10H_MMIO_CONF_ENABLE		(1<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) #define FAM10H_MMIO_CONF_BUSRANGE_MASK	0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) #define FAM10H_MMIO_CONF_BUSRANGE_SHIFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) #define FAM10H_MMIO_CONF_BASE_MASK	0xfffffffULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) #define FAM10H_MMIO_CONF_BASE_SHIFT	20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) #define MSR_FAM10H_NODE_ID		0xc001100c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) #define MSR_F10H_DECFG			0xc0011029
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) #define MSR_F10H_DECFG_LFENCE_SERIALIZE_BIT	1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) #define MSR_F10H_DECFG_LFENCE_SERIALIZE		BIT_ULL(MSR_F10H_DECFG_LFENCE_SERIALIZE_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) /* K8 MSRs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) #define MSR_K8_TOP_MEM1			0xc001001a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) #define MSR_K8_TOP_MEM2			0xc001001d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) #define MSR_K8_SYSCFG			0xc0010010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) #define MSR_K8_SYSCFG_MEM_ENCRYPT_BIT	23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) #define MSR_K8_SYSCFG_MEM_ENCRYPT	BIT_ULL(MSR_K8_SYSCFG_MEM_ENCRYPT_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) #define MSR_K8_INT_PENDING_MSG		0xc0010055
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) /* C1E active bits in int pending message */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) #define K8_INTP_C1E_ACTIVE_MASK		0x18000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) #define MSR_K8_TSEG_ADDR		0xc0010112
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) #define MSR_K8_TSEG_MASK		0xc0010113
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) #define K8_MTRRFIXRANGE_DRAM_ENABLE	0x00040000 /* MtrrFixDramEn bit    */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) #define K8_MTRRFIXRANGE_DRAM_MODIFY	0x00080000 /* MtrrFixDramModEn bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) #define K8_MTRR_RDMEM_WRMEM_MASK	0x18181818 /* Mask: RdMem|WrMem    */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) /* K7 MSRs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) #define MSR_K7_EVNTSEL0			0xc0010000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) #define MSR_K7_PERFCTR0			0xc0010004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) #define MSR_K7_EVNTSEL1			0xc0010001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) #define MSR_K7_PERFCTR1			0xc0010005
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) #define MSR_K7_EVNTSEL2			0xc0010002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) #define MSR_K7_PERFCTR2			0xc0010006
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) #define MSR_K7_EVNTSEL3			0xc0010003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) #define MSR_K7_PERFCTR3			0xc0010007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) #define MSR_K7_CLK_CTL			0xc001001b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) #define MSR_K7_HWCR			0xc0010015
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) #define MSR_K7_HWCR_SMMLOCK_BIT		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) #define MSR_K7_HWCR_SMMLOCK		BIT_ULL(MSR_K7_HWCR_SMMLOCK_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) #define MSR_K7_HWCR_IRPERF_EN_BIT	30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) #define MSR_K7_HWCR_IRPERF_EN		BIT_ULL(MSR_K7_HWCR_IRPERF_EN_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) #define MSR_K7_FID_VID_CTL		0xc0010041
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) #define MSR_K7_FID_VID_STATUS		0xc0010042
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) /* K6 MSRs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) #define MSR_K6_WHCR			0xc0000082
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) #define MSR_K6_UWCCR			0xc0000085
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) #define MSR_K6_EPMR			0xc0000086
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) #define MSR_K6_PSOR			0xc0000087
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) #define MSR_K6_PFIR			0xc0000088
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) /* Centaur-Hauls/IDT defined MSRs. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) #define MSR_IDT_FCR1			0x00000107
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) #define MSR_IDT_FCR2			0x00000108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) #define MSR_IDT_FCR3			0x00000109
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) #define MSR_IDT_FCR4			0x0000010a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) #define MSR_IDT_MCR0			0x00000110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) #define MSR_IDT_MCR1			0x00000111
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) #define MSR_IDT_MCR2			0x00000112
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) #define MSR_IDT_MCR3			0x00000113
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) #define MSR_IDT_MCR4			0x00000114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) #define MSR_IDT_MCR5			0x00000115
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) #define MSR_IDT_MCR6			0x00000116
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) #define MSR_IDT_MCR7			0x00000117
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) #define MSR_IDT_MCR_CTRL		0x00000120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) /* VIA Cyrix defined MSRs*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) #define MSR_VIA_FCR			0x00001107
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) #define MSR_VIA_LONGHAUL		0x0000110a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) #define MSR_VIA_RNG			0x0000110b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) #define MSR_VIA_BCR2			0x00001147
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) /* Transmeta defined MSRs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) #define MSR_TMTA_LONGRUN_CTRL		0x80868010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) #define MSR_TMTA_LONGRUN_FLAGS		0x80868011
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) #define MSR_TMTA_LRTI_READOUT		0x80868018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) #define MSR_TMTA_LRTI_VOLT_MHZ		0x8086801a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) /* Intel defined MSRs. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) #define MSR_IA32_P5_MC_ADDR		0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) #define MSR_IA32_P5_MC_TYPE		0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) #define MSR_IA32_TSC			0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) #define MSR_IA32_PLATFORM_ID		0x00000017
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) #define MSR_IA32_EBL_CR_POWERON		0x0000002a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) #define MSR_EBC_FREQUENCY_ID		0x0000002c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) #define MSR_SMI_COUNT			0x00000034
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) /* Referred to as IA32_FEATURE_CONTROL in Intel's SDM. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) #define MSR_IA32_FEAT_CTL		0x0000003a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) #define FEAT_CTL_LOCKED				BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) #define FEAT_CTL_VMX_ENABLED_INSIDE_SMX		BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) #define FEAT_CTL_VMX_ENABLED_OUTSIDE_SMX	BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) #define FEAT_CTL_LMCE_ENABLED			BIT(20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) #define MSR_IA32_TSC_ADJUST             0x0000003b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) #define MSR_IA32_BNDCFGS		0x00000d90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) #define MSR_IA32_BNDCFGS_RSVD		0x00000ffc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) #define MSR_IA32_XSS			0x00000da0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) #define MSR_IA32_APICBASE		0x0000001b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) #define MSR_IA32_APICBASE_BSP		(1<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) #define MSR_IA32_APICBASE_ENABLE	(1<<11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) #define MSR_IA32_APICBASE_BASE		(0xfffff<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) #define MSR_IA32_TSCDEADLINE		0x000006e0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) #define MSR_IA32_UCODE_WRITE		0x00000079
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) #define MSR_IA32_UCODE_REV		0x0000008b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) #define MSR_IA32_SMM_MONITOR_CTL	0x0000009b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) #define MSR_IA32_SMBASE			0x0000009e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) #define MSR_IA32_PERF_STATUS		0x00000198
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) #define MSR_IA32_PERF_CTL		0x00000199
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) #define INTEL_PERF_CTL_MASK		0xffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) #define MSR_IA32_MPERF			0x000000e7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) #define MSR_IA32_APERF			0x000000e8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) #define MSR_IA32_THERM_CONTROL		0x0000019a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) #define MSR_IA32_THERM_INTERRUPT	0x0000019b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) #define THERM_INT_HIGH_ENABLE		(1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) #define THERM_INT_LOW_ENABLE		(1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) #define THERM_INT_PLN_ENABLE		(1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) #define MSR_IA32_THERM_STATUS		0x0000019c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) #define THERM_STATUS_PROCHOT		(1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) #define THERM_STATUS_POWER_LIMIT	(1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) #define MSR_THERM2_CTL			0x0000019d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) #define MSR_THERM2_CTL_TM_SELECT	(1ULL << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) #define MSR_IA32_MISC_ENABLE		0x000001a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) #define MSR_IA32_TEMPERATURE_TARGET	0x000001a2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) #define MSR_MISC_FEATURE_CONTROL	0x000001a4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) #define MSR_MISC_PWR_MGMT		0x000001aa
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) #define MSR_IA32_ENERGY_PERF_BIAS	0x000001b0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) #define ENERGY_PERF_BIAS_PERFORMANCE		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) #define ENERGY_PERF_BIAS_BALANCE_PERFORMANCE	4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) #define ENERGY_PERF_BIAS_NORMAL			6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) #define ENERGY_PERF_BIAS_BALANCE_POWERSAVE	8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) #define ENERGY_PERF_BIAS_POWERSAVE		15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) #define MSR_IA32_PACKAGE_THERM_STATUS		0x000001b1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) #define PACKAGE_THERM_STATUS_PROCHOT		(1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) #define PACKAGE_THERM_STATUS_POWER_LIMIT	(1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) #define MSR_IA32_PACKAGE_THERM_INTERRUPT	0x000001b2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) #define PACKAGE_THERM_INT_HIGH_ENABLE		(1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) #define PACKAGE_THERM_INT_LOW_ENABLE		(1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) #define PACKAGE_THERM_INT_PLN_ENABLE		(1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) /* Thermal Thresholds Support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) #define THERM_INT_THRESHOLD0_ENABLE    (1 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) #define THERM_SHIFT_THRESHOLD0        8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) #define THERM_MASK_THRESHOLD0          (0x7f << THERM_SHIFT_THRESHOLD0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) #define THERM_INT_THRESHOLD1_ENABLE    (1 << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) #define THERM_SHIFT_THRESHOLD1        16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) #define THERM_MASK_THRESHOLD1          (0x7f << THERM_SHIFT_THRESHOLD1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) #define THERM_STATUS_THRESHOLD0        (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) #define THERM_LOG_THRESHOLD0           (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) #define THERM_STATUS_THRESHOLD1        (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) #define THERM_LOG_THRESHOLD1           (1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) /* MISC_ENABLE bits: architectural */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) #define MSR_IA32_MISC_ENABLE_FAST_STRING_BIT		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) #define MSR_IA32_MISC_ENABLE_FAST_STRING		(1ULL << MSR_IA32_MISC_ENABLE_FAST_STRING_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) #define MSR_IA32_MISC_ENABLE_TCC_BIT			1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) #define MSR_IA32_MISC_ENABLE_TCC			(1ULL << MSR_IA32_MISC_ENABLE_TCC_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) #define MSR_IA32_MISC_ENABLE_EMON_BIT			7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) #define MSR_IA32_MISC_ENABLE_EMON			(1ULL << MSR_IA32_MISC_ENABLE_EMON_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) #define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL_BIT		11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) #define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL		(1ULL << MSR_IA32_MISC_ENABLE_BTS_UNAVAIL_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) #define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL_BIT		12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) #define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL		(1ULL << MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) #define MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP_BIT	16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) #define MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP		(1ULL << MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) #define MSR_IA32_MISC_ENABLE_MWAIT_BIT			18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) #define MSR_IA32_MISC_ENABLE_MWAIT			(1ULL << MSR_IA32_MISC_ENABLE_MWAIT_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) #define MSR_IA32_MISC_ENABLE_LIMIT_CPUID_BIT		22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) #define MSR_IA32_MISC_ENABLE_LIMIT_CPUID		(1ULL << MSR_IA32_MISC_ENABLE_LIMIT_CPUID_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) #define MSR_IA32_MISC_ENABLE_XTPR_DISABLE_BIT		23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) #define MSR_IA32_MISC_ENABLE_XTPR_DISABLE		(1ULL << MSR_IA32_MISC_ENABLE_XTPR_DISABLE_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) #define MSR_IA32_MISC_ENABLE_XD_DISABLE_BIT		34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) #define MSR_IA32_MISC_ENABLE_XD_DISABLE			(1ULL << MSR_IA32_MISC_ENABLE_XD_DISABLE_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) /* MISC_ENABLE bits: model-specific, meaning may vary from core to core */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) #define MSR_IA32_MISC_ENABLE_X87_COMPAT_BIT		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) #define MSR_IA32_MISC_ENABLE_X87_COMPAT			(1ULL << MSR_IA32_MISC_ENABLE_X87_COMPAT_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) #define MSR_IA32_MISC_ENABLE_TM1_BIT			3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) #define MSR_IA32_MISC_ENABLE_TM1			(1ULL << MSR_IA32_MISC_ENABLE_TM1_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) #define MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE_BIT	4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) #define MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE		(1ULL << MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) #define MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE_BIT	6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) #define MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE		(1ULL << MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) #define MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK_BIT		8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) #define MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK		(1ULL << MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) #define MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT	9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) #define MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE		(1ULL << MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) #define MSR_IA32_MISC_ENABLE_FERR_BIT			10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) #define MSR_IA32_MISC_ENABLE_FERR			(1ULL << MSR_IA32_MISC_ENABLE_FERR_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) #define MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX_BIT		10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) #define MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX		(1ULL << MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) #define MSR_IA32_MISC_ENABLE_TM2_BIT			13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) #define MSR_IA32_MISC_ENABLE_TM2			(1ULL << MSR_IA32_MISC_ENABLE_TM2_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) #define MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE_BIT	19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) #define MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE		(1ULL << MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) #define MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK_BIT		20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) #define MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK		(1ULL << MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) #define MSR_IA32_MISC_ENABLE_L1D_CONTEXT_BIT		24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) #define MSR_IA32_MISC_ENABLE_L1D_CONTEXT		(1ULL << MSR_IA32_MISC_ENABLE_L1D_CONTEXT_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) #define MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE_BIT	37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) #define MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE		(1ULL << MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) #define MSR_IA32_MISC_ENABLE_TURBO_DISABLE_BIT		38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) #define MSR_IA32_MISC_ENABLE_TURBO_DISABLE		(1ULL << MSR_IA32_MISC_ENABLE_TURBO_DISABLE_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) #define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE_BIT	39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) #define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE		(1ULL << MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) /* MISC_FEATURES_ENABLES non-architectural features */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) #define MSR_MISC_FEATURES_ENABLES	0x00000140
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) #define MSR_MISC_FEATURES_ENABLES_CPUID_FAULT_BIT	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) #define MSR_MISC_FEATURES_ENABLES_CPUID_FAULT		BIT_ULL(MSR_MISC_FEATURES_ENABLES_CPUID_FAULT_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) #define MSR_MISC_FEATURES_ENABLES_RING3MWAIT_BIT	1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) #define MSR_IA32_TSC_DEADLINE		0x000006E0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) #define MSR_TSX_FORCE_ABORT		0x0000010F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) #define MSR_TFA_RTM_FORCE_ABORT_BIT	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) #define MSR_TFA_RTM_FORCE_ABORT		BIT_ULL(MSR_TFA_RTM_FORCE_ABORT_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) /* P4/Xeon+ specific */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) #define MSR_IA32_MCG_EAX		0x00000180
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) #define MSR_IA32_MCG_EBX		0x00000181
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) #define MSR_IA32_MCG_ECX		0x00000182
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) #define MSR_IA32_MCG_EDX		0x00000183
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) #define MSR_IA32_MCG_ESI		0x00000184
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) #define MSR_IA32_MCG_EDI		0x00000185
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) #define MSR_IA32_MCG_EBP		0x00000186
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) #define MSR_IA32_MCG_ESP		0x00000187
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) #define MSR_IA32_MCG_EFLAGS		0x00000188
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) #define MSR_IA32_MCG_EIP		0x00000189
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) #define MSR_IA32_MCG_RESERVED		0x0000018a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) /* Pentium IV performance counter MSRs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) #define MSR_P4_BPU_PERFCTR0		0x00000300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) #define MSR_P4_BPU_PERFCTR1		0x00000301
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) #define MSR_P4_BPU_PERFCTR2		0x00000302
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) #define MSR_P4_BPU_PERFCTR3		0x00000303
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) #define MSR_P4_MS_PERFCTR0		0x00000304
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) #define MSR_P4_MS_PERFCTR1		0x00000305
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) #define MSR_P4_MS_PERFCTR2		0x00000306
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) #define MSR_P4_MS_PERFCTR3		0x00000307
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) #define MSR_P4_FLAME_PERFCTR0		0x00000308
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) #define MSR_P4_FLAME_PERFCTR1		0x00000309
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) #define MSR_P4_FLAME_PERFCTR2		0x0000030a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) #define MSR_P4_FLAME_PERFCTR3		0x0000030b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) #define MSR_P4_IQ_PERFCTR0		0x0000030c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) #define MSR_P4_IQ_PERFCTR1		0x0000030d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) #define MSR_P4_IQ_PERFCTR2		0x0000030e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) #define MSR_P4_IQ_PERFCTR3		0x0000030f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) #define MSR_P4_IQ_PERFCTR4		0x00000310
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) #define MSR_P4_IQ_PERFCTR5		0x00000311
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) #define MSR_P4_BPU_CCCR0		0x00000360
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) #define MSR_P4_BPU_CCCR1		0x00000361
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) #define MSR_P4_BPU_CCCR2		0x00000362
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) #define MSR_P4_BPU_CCCR3		0x00000363
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) #define MSR_P4_MS_CCCR0			0x00000364
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) #define MSR_P4_MS_CCCR1			0x00000365
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) #define MSR_P4_MS_CCCR2			0x00000366
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) #define MSR_P4_MS_CCCR3			0x00000367
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) #define MSR_P4_FLAME_CCCR0		0x00000368
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) #define MSR_P4_FLAME_CCCR1		0x00000369
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) #define MSR_P4_FLAME_CCCR2		0x0000036a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) #define MSR_P4_FLAME_CCCR3		0x0000036b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) #define MSR_P4_IQ_CCCR0			0x0000036c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) #define MSR_P4_IQ_CCCR1			0x0000036d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) #define MSR_P4_IQ_CCCR2			0x0000036e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) #define MSR_P4_IQ_CCCR3			0x0000036f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) #define MSR_P4_IQ_CCCR4			0x00000370
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) #define MSR_P4_IQ_CCCR5			0x00000371
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) #define MSR_P4_ALF_ESCR0		0x000003ca
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) #define MSR_P4_ALF_ESCR1		0x000003cb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) #define MSR_P4_BPU_ESCR0		0x000003b2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) #define MSR_P4_BPU_ESCR1		0x000003b3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) #define MSR_P4_BSU_ESCR0		0x000003a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) #define MSR_P4_BSU_ESCR1		0x000003a1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) #define MSR_P4_CRU_ESCR0		0x000003b8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) #define MSR_P4_CRU_ESCR1		0x000003b9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) #define MSR_P4_CRU_ESCR2		0x000003cc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) #define MSR_P4_CRU_ESCR3		0x000003cd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) #define MSR_P4_CRU_ESCR4		0x000003e0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) #define MSR_P4_CRU_ESCR5		0x000003e1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) #define MSR_P4_DAC_ESCR0		0x000003a8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) #define MSR_P4_DAC_ESCR1		0x000003a9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) #define MSR_P4_FIRM_ESCR0		0x000003a4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) #define MSR_P4_FIRM_ESCR1		0x000003a5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) #define MSR_P4_FLAME_ESCR0		0x000003a6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) #define MSR_P4_FLAME_ESCR1		0x000003a7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) #define MSR_P4_FSB_ESCR0		0x000003a2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) #define MSR_P4_FSB_ESCR1		0x000003a3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) #define MSR_P4_IQ_ESCR0			0x000003ba
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) #define MSR_P4_IQ_ESCR1			0x000003bb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) #define MSR_P4_IS_ESCR0			0x000003b4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) #define MSR_P4_IS_ESCR1			0x000003b5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) #define MSR_P4_ITLB_ESCR0		0x000003b6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) #define MSR_P4_ITLB_ESCR1		0x000003b7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) #define MSR_P4_IX_ESCR0			0x000003c8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) #define MSR_P4_IX_ESCR1			0x000003c9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) #define MSR_P4_MOB_ESCR0		0x000003aa
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) #define MSR_P4_MOB_ESCR1		0x000003ab
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) #define MSR_P4_MS_ESCR0			0x000003c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) #define MSR_P4_MS_ESCR1			0x000003c1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) #define MSR_P4_PMH_ESCR0		0x000003ac
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) #define MSR_P4_PMH_ESCR1		0x000003ad
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) #define MSR_P4_RAT_ESCR0		0x000003bc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) #define MSR_P4_RAT_ESCR1		0x000003bd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) #define MSR_P4_SAAT_ESCR0		0x000003ae
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) #define MSR_P4_SAAT_ESCR1		0x000003af
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) #define MSR_P4_SSU_ESCR0		0x000003be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) #define MSR_P4_SSU_ESCR1		0x000003bf /* guess: not in manual */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) #define MSR_P4_TBPU_ESCR0		0x000003c2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) #define MSR_P4_TBPU_ESCR1		0x000003c3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) #define MSR_P4_TC_ESCR0			0x000003c4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) #define MSR_P4_TC_ESCR1			0x000003c5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) #define MSR_P4_U2L_ESCR0		0x000003b0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) #define MSR_P4_U2L_ESCR1		0x000003b1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) #define MSR_P4_PEBS_MATRIX_VERT		0x000003f2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) /* Intel Core-based CPU performance counters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) #define MSR_CORE_PERF_FIXED_CTR0	0x00000309
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) #define MSR_CORE_PERF_FIXED_CTR1	0x0000030a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) #define MSR_CORE_PERF_FIXED_CTR2	0x0000030b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) #define MSR_CORE_PERF_FIXED_CTR3	0x0000030c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) #define MSR_CORE_PERF_FIXED_CTR_CTRL	0x0000038d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) #define MSR_CORE_PERF_GLOBAL_STATUS	0x0000038e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) #define MSR_CORE_PERF_GLOBAL_CTRL	0x0000038f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) #define MSR_CORE_PERF_GLOBAL_OVF_CTRL	0x00000390
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) #define MSR_PERF_METRICS		0x00000329
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) /* PERF_GLOBAL_OVF_CTL bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) #define MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI_BIT	55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) #define MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI		(1ULL << MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) #define MSR_CORE_PERF_GLOBAL_OVF_CTRL_OVF_BUF_BIT		62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) #define MSR_CORE_PERF_GLOBAL_OVF_CTRL_OVF_BUF			(1ULL <<  MSR_CORE_PERF_GLOBAL_OVF_CTRL_OVF_BUF_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) #define MSR_CORE_PERF_GLOBAL_OVF_CTRL_COND_CHGD_BIT		63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) #define MSR_CORE_PERF_GLOBAL_OVF_CTRL_COND_CHGD			(1ULL << MSR_CORE_PERF_GLOBAL_OVF_CTRL_COND_CHGD_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) /* Geode defined MSRs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) #define MSR_GEODE_BUSCONT_CONF0		0x00001900
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) /* Intel VT MSRs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) #define MSR_IA32_VMX_BASIC              0x00000480
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) #define MSR_IA32_VMX_PINBASED_CTLS      0x00000481
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) #define MSR_IA32_VMX_PROCBASED_CTLS     0x00000482
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) #define MSR_IA32_VMX_EXIT_CTLS          0x00000483
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) #define MSR_IA32_VMX_ENTRY_CTLS         0x00000484
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) #define MSR_IA32_VMX_MISC               0x00000485
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) #define MSR_IA32_VMX_CR0_FIXED0         0x00000486
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) #define MSR_IA32_VMX_CR0_FIXED1         0x00000487
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) #define MSR_IA32_VMX_CR4_FIXED0         0x00000488
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) #define MSR_IA32_VMX_CR4_FIXED1         0x00000489
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) #define MSR_IA32_VMX_VMCS_ENUM          0x0000048a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) #define MSR_IA32_VMX_PROCBASED_CTLS2    0x0000048b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) #define MSR_IA32_VMX_EPT_VPID_CAP       0x0000048c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) #define MSR_IA32_VMX_TRUE_PINBASED_CTLS  0x0000048d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) #define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x0000048e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) #define MSR_IA32_VMX_TRUE_EXIT_CTLS      0x0000048f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) #define MSR_IA32_VMX_TRUE_ENTRY_CTLS     0x00000490
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) #define MSR_IA32_VMX_VMFUNC             0x00000491
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) /* VMX_BASIC bits and bitmasks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) #define VMX_BASIC_VMCS_SIZE_SHIFT	32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) #define VMX_BASIC_TRUE_CTLS		(1ULL << 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) #define VMX_BASIC_64		0x0001000000000000LLU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) #define VMX_BASIC_MEM_TYPE_SHIFT	50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) #define VMX_BASIC_MEM_TYPE_MASK	0x003c000000000000LLU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) #define VMX_BASIC_MEM_TYPE_WB	6LLU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) #define VMX_BASIC_INOUT		0x0040000000000000LLU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) /* MSR_IA32_VMX_MISC bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) #define MSR_IA32_VMX_MISC_INTEL_PT                 (1ULL << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) #define MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS (1ULL << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) #define MSR_IA32_VMX_MISC_PREEMPTION_TIMER_SCALE   0x1F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) /* AMD-V MSRs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) #define MSR_VM_CR                       0xc0010114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) #define MSR_VM_IGNNE                    0xc0010115
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) #define MSR_VM_HSAVE_PA                 0xc0010117
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) #endif /* _ASM_X86_MSR_INDEX_H */